Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-15
2007-05-15
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
10937726
ABSTRACT:
Disclosed is a method of simulating semiconductor circuitry in which trace data received from a first simulation of the semiconductor circuitry, is processed and the values of inputs to the semiconductor circuitry read from the trace data are output to a second simulation of semiconductor circuitry. There is also disclosed a method of determining whether first and second simulations of semiconductor circuitry are equivalent in which transitions in the values of registers simulated by the first and second simulations are analysed, and an error is declared if, following a register in either simulation making a transition to a value which is not equivalent to the corresponding register in the other simulation. The value of the register in the same simulation makes a further transition to a non-equivalent value before the value of the register in the other simulation makes a transition to an equivalent value.
REFERENCES:
patent: 6618839 (2003-09-01), Beardslee et al.
patent: 6885983 (2005-04-01), Ho et al.
patent: 2003/0225565 (2003-12-01), Garcia et al.
patent: 2004/0122644 (2004-06-01), Neifert et al.
patent: 2004/0194046 (2004-09-01), Singhal et al.
Murray Robert Mark Alistair
Stoye William Robert
Barnes & Thornburg LLP
Garbowski Leigh M.
Tenison Technology EDA Limited
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