Comparison circuit utilizing a differential amplifier

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

36518907, 327202, 327208, 327 52, 327 54, G11C 1100

Patent

active

059739550

ABSTRACT:
A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells. A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) uses both a differential amplifier (360) included within a D-flip-flop circuit (114) and a reference voltage provided by a reference voltage circuit (365) to compare addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

REFERENCES:
patent: 4607172 (1986-08-01), Frederiksen et al.
patent: 5196737 (1993-03-01), Olmstead
patent: 5204560 (1993-04-01), Bredin et al.
patent: 5310311 (1992-04-01), Voorman et al.
patent: 5625308 (1997-04-01), Matsumoto et al.

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