Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-11
2008-12-30
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07472370
ABSTRACT:
A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For each of the tiles, a specification is input of a graphical tile representation and connection representations that terminate at a boundary of the tile representation. A specification is input of an arrayed placement of occurrences of the tile representations. For each abutting pair of occurrences of the tile representations in the arrayed placement, the connection representations are determined that terminate at a shared portion of the boundaries of the tile representations of the abutting pair. For each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, a match is checked between the connection representations terminating at the position.
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Barei James F.
Bean Keith R.
Kirkwood Daniel P.
Ralston Benjamin D.
Reynolds Bart
Lin Sun J
Liu Justin
Maunu LeRoy D.
Xilinx , Inc.
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