Compare, select, sort, and median-filter apparatus in...

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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C326S038000, C326S046000

Reexamination Certificate

active

06987401

ABSTRACT:
A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The selector circuitry provides one of the two inputs of the logic element as an output in response to a selection signal. The selection signal for all logic elements (i.e., logic elements 1 through N) constitutes the compare output signal of the Nth logic element. A median-calculation apparatus is also disclosed. The median-filter apparatus includes at least one insertion-sort circuitry. The at least one insertion-sort circuitry performs insertion-sorting of a set of input numbers corresponding to that insertion-sort circuitry to generate a corresponding set of sorted numbers. Each of the sorted set of numbers includes a median value of the corresponding set of input numbers.

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patent: 5900006 (1999-05-01), Yoon
Copending U.S. Appl. No. 10/212,487, filed Aug. 5, 2002, “Method And Apparatus For Implementing A Viterbi Decoder,” (ALT.P004).
Copending U.S. Appl. No. 10/331,707, filed Dec. 30, 2002, “Method And Apparatus For Implementing A Multiple Constraint Length Viterbi Decoder,” (ALT.P013).
John Smith, “Implementing Median Filters In XC4000E PFGAs,” Design Hints and Issues, Xilinx, (available on the Internet before the filing of the present patent application), 1 pg., no date.
Altera, Apex 20K, “Programmable Logic Device Family,” Data Sheet, Ver. 4,3, Feb. 2002, pp. 1-116.
Altera, Apex 20KC, “Programmable Logic Device,” Data Sheet, Ver. 2.1, Apr. 2002, pp. 1-87.

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