Comparator having reduced offset voltage

Details Comparator having reduced offset voltage Comparator having reduced offset voltage

1999-06-01

2001-02-06

Hardy, David (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S402000

Reexamination Certificate

active

06184558

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and more particularly relates to a comparator circuit formed using a MOS type transistor.
A comparator circuit formed using a MOS type transistor has conventionally been widely used. There is known a comparator having a MOS type transistor with a wide channel width and a long channel length to obtain a comparator having a small offset voltage.
However, in the conventional comparator circuit formed using the MOS type transistor, increasing the channel width and the channel length of the MOS type transistor is generally done to reduce the offset voltage. Therefore, a problem exists in which the area of the comparator is increased.
An object of the present invention is to provide a comparator having a small offset voltage and occupying a small area, which nobody has been able to achieve with a conventional comparator using a MOS type transistor.
SUMMARY OF THE INVENTION
The present invention uses the following means to achieve the above object.
(1) A mutual conductance gm of a MOS type transistor on a load side is set to be smaller than a mutual conductance gm of a MOS type transistor on a differential side in a comparator constructed by MOS type transistors.
(2) Mobility of the MOS type transistor on the load side is set to be smaller than mobility of the MOS type transistor on the differential side in this comparator.
(3) The impurity concentration of a channel area of the MOS type transistor on the load side is set to be higher than that of the MOS type transistor on the differential side in this comparator.
(4) A threshold voltage of the MOS type transistor on the load side is set to be higher than the threshold voltage of the MOS type transistor on the differential side in this comparator.
(5) The thickness of a gate oxide film of the MOS type transistor on the load side is set to be thicker than the thickness of a gate oxide film of the MOS type transistor on the differential side in this comparator.
(6) The MOS type transistor on the load side is a P−type transistor and the MOS type transistor on the differential side is an N−type transistor in this comparator.
(7) The MOS type transistor on the load side is an N−type transistor and the MOS type transistor on the differential side is a P−type transistor in this comparator.
(8) Impurities introduced into the channel areas of the MOS type transistors are phosphorus.
(9) The impurities introduced into the channel areas of the MOS type transistors are arsenic.
(10) The impurities introduced into the channel areas of the MOS type transistors are boron.
(11) The impurities introduced into the channel areas of the MOS type transistors are BF2.
(12) Two or more kinds of impurities are introduced into the channel areas of the MOS type transistors.
(13) No gate electrode overlaps with a source diffusive layer and a drain diffusive layer formed within a substrate only in the MOS type transistor on the load side in this comparator.
(14) A well area of a second conductivity type is formed within a silicon semiconductor substrate of a first conductivity type, and a MOS type transistor on this load side is formed within a well of this second conductivity type, and a MOS type transistor on this differential side is formed outside the well area of this second conductivity type.
(15) A well area of a second conductivity type is formed within a silicon semiconductor substrate of a first conductivity type, and the MOS type transistor on the differential side is formed within the well of the second conductivity type, and the MOS type transistor on the load side is formed outside the well area of the second conductivity type.
(16) well areas of second and third conductivity types are formed within a silicon semiconductor substrate of a first conductivity type, and the MOS type transistors on the differential side and the load side are formed within the respective wells.


REFERENCES:
patent: 4809227 (1989-02-01), Suzuki et al.

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