Comparator circuit with built-in hysteresis offset

Details Comparator circuit with built-in hysteresis offset Comparator circuit with built-in hysteresis offset

1999-06-04

2001-03-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S205000, C327S065000, C327S067000

Reexamination Certificate

active

06208187

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to electronic circuits used as comparators, and more specifically to electronic circuits used as comparators with built-in hysteresis.
The problem addressed by this invention is encountered in electronic circuits used to compare a first voltage to a second voltage. Commercially available comparators, such as the LM2904, are readily available and are often used to compare voltages. The LM2904 comparator is designed for no hysteresis and low offset. In some applications, such as a reset circuit, however, it is desirable for a comparator to have more hysteresis.
FIG. 1
shows a prior art comparator, such as the LM2904, configured to have hysteresis. More specifically,
FIG. 1
shows comparator
10
having a non-inverting input
4
, an inverting input
12
, and an output
8
. Resistor
6
and resistor
3
add hysteresis to the circuit, as is known in the art. Typical resistor values for this configuration are 10 kilohms for resistor
3
and 1 Megohms for resistor
6
. In fact, problems with the circuit of
FIG. 1
are that large resistor values are required and/or the circuit has an undesirably low gain. Large resistor values are inconvenient for integration onto a chip.
FIG. 2
a
shows a prior art comparator circuit
16
. This circuit includes a bias circuit
18
, a differential input stage
20
, and a hysteresis circuit
22
. The bias circuit includes current source
24
connected in series with NPN bipolar transistor
26
and resistor
28
. In operation, current is generated by current source
24
to forward bias transistor
26
. This creates a bias voltage which is used by the transistors in the differential input stage
20
and by transistor
48
of comparator
16
.
The differential stage includes PNP transistors
30
,
36
,
40
, and
44
, NPN transistors
32
and
46
, resistors
38
and
42
, and current source
34
. In operation, the base of transistor
36
is the noninverting input of comparator
16
and the base of transistor
40
is the inverting input. When the base of transistor
36
is at a higher voltage than the base of transistor
40
, transistor
40
turns on and conducts the current supplied by current source
34
while transistor
36
is off. Consequently, transistor
46
is turned off which allows transistor
44
to drive the voltage on Vout high. Conversely, if the base of transistor
36
is lower than the base of transistor
40
, then transistor
36
is on and transistor
40
is off. This condition drives the emitter of transistor
46
low which turns transistor
46
on. Since transistor
46
is on, Vout is driven to a low voltage.
The hysteresis circuit
22
includes PNP transistor
48
and resistor
50
. In operation, transistor
48
turns on when the V− input of the comparator is at a sufficiently low value to turn on transistors
30
,
32
and
40
. When the V− input goes positive with respect to the V+ input, transistor
36
conducts, turning off transistors
32
,
30
and
48
. With transistor
48
on, a voltage drop is developed across resistor
50
. Therefore, this additional voltage drop is the hysteresis which must be overcome to switch the comparator when the voltage on the V− input rises.
The problem with the prior art of
FIG. 2
a
is that the circuit requires resistors
38
and
42
to be relatively low resistance so that the circuit can have sufficient dynamic range without the transistors in the differential stage operating in saturation. Consequently, the circuit in
FIG. 2
a
suffers from low gain.
FIG. 2
b
shows a circuit which is similar to
FIG. 2
a
but differs in how the hysteresis in the circuit is achieved.
FIG. 2
b
shows a bias current circuit comprising transistor M
18
, Q
29
, and resistor R
40
. The differential input stage comprises transistors Q
0
, Q
1
, Q
2
, Q
3
, Q
4
, and Q
5
. The output stage comprises M
15
and M
19
. M
13
, M
14
, M
15
, M
16
, and M
51
are current sources for the circuit. The base of Q
2
is the non-inverting input and the base of Q
0
is the inverting input of the differential stage. Resistors R
26
, R
29
, and R
38
form a voltage divider to set up the voltage reference for the non-inverting input and to form the hysteresis circuit.
In operation, the output of the circuit, Vout, switches when the input, V−, rises to the threshold voltage of the circuit. At that point, Q
0
and Q
1
turn off while transistors Q
3
and Q
2
turn on. With Q
3
on, M
36
and M
19
are turned on thereby activating the hysteresis circuit and pulling the output to a low voltage, respectively. The hysteresis circuit is activated by transistor M
36
effectively shorting resistor R
38
which effectively changes the voltage reference on the inverting input. The problem with this circuit is that current is always flowing in through the voltage divider network. Additionally, there is a practical problem with making transistor M
36
large enough to completely short out the resistor R
38
unless resistor R
38
is made extremely large. If resistor R
38
is large, then typically resistors R
26
and R
29
will have to be even larger and, for an integrated circuit, large circuit areas will be used.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a comparator characterized as having high gain.
It is further an object of this invention to provide a comparator which does not require a large resistor and, therefore, does not require a large area for the resistor on an integrated circuit.
Therefore, according to the present invention, a high-gain comparator having built-in offset comprises several functional blocks, including: a differential amplifier pair, an offset voltage element, an output generation element, and a control element. The differential amplifier pair has first and second elements, such as transistors, that receive first and second input voltages. The offset voltage element creates an offset voltage between the first and second elements of the differential amplifier pair. The output generation element is operably coupled to the differential amplifier pair and generates an output voltage of the comparator that is indicative of a voltage difference between the first and second input voltages. The control element is operably coupled to the output signal and controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.


REFERENCES:
patent: 5465070 (1995-11-01), Koyama et al.
patent: 5528185 (1996-06-01), Lewicki et al.
patent: 5587674 (1996-12-01), Danstrom
patent: 5589785 (1996-12-01), Garavan
patent: 5656957 (1997-08-01), Marlow et al.
patent: 5801553 (1998-09-01), Danstrom
patent: 5955899 (1999-09-01), Afghahi

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