Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Patent
1995-02-08
1997-01-28
Westin, Edward P.
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
326113, 365 49, H03K 19094
Patent
active
055981151
ABSTRACT:
A content-addressable memory wherein match transistors are prevented from discharging a match line by either placing transistors in series with the match transistors and only turning them on during a match sensing period, or a match sense line which is driven near the precharge voltage of the match line until the match sensing period. The match sensing line also provides charging current to recharge the match line. For some applications, a differential match line amplifier is used to detect matches and mismatches. The match sense line can be used with a CAM having a four-transistor comparator. The invention is also applicable to match lines in programmable-array logic (PAL) cells, and for either NMOS or PMOS circuits.
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patent: 5051948 (1991-09-01), Watabe et al.
patent: 5226005 (1993-07-01), Lee et al.
Weste et al.; "Principles of CMOS VLSI Design"; .COPYRGT.1985 by AT&T Bell Laboratories, Inc. and Kamran Eshraghian; pp. 162-163.
Seitz et al.; "Hot-Clock nMOS"; paper presented at the 1985 Chapel Hill Conference on VLSI.
Albert Philip H.
Driscoll Benjamin D.
Intergraph Corporation
Westin Edward P.
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