Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-07-11
2004-05-11
Tran, Khai (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000
Reexamination Certificate
active
06735265
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a comparator for comparing the frequencies of two binary signals and outputting a phase difference of the two signals.
BACKGROUND OF THE INVENTION
As a phase comparator to compare the phases of two binary signals, a method using an exclusive-OR circuit is well known. In this case, when two binary signals are supplied to two input ports of the exclusive-OR circuit, a duty cycle (pulse width) in a binary output signal changes in proportion to a phase difference of the two input signals. Accordingly, the duty cycle is averaged by an integrator and an analog signal based on the phase difference is extracted.
The exclusive-OR circuit can detect the phase difference in case each frequency of two input signals are equal and a range of the phase difference is “−&pgr;~&pgr;”. In short, the exclusive-OR circuit can not correctly detect the phase difference at operation of frequency step. Accordingly, if the exclusive-OR circuit is used as the phase comparator and an oscillation frequency of voltage control oscillator is controlled by the detected phase difference, i. e., if PLL (phase locked loop) circuit of this type is composed, a settling time (a time required for initial drop) becomes long.
On the other hand, the phase comparator whose range of phase difference is expanded as “−2&pgr;~2&pgr;” is known. This phase comparator operates so that output value of phase difference maintains “−2&pgr;” or “2&pgr;” in case the phase difference is over the range of “−2&pgr;~2&pgr;”. Therefore, it is expected that this phase comparator correctly operates at operation of frequency step. However, even if the range of phase difference is expanded, the range is limited as “−2&pgr;~2&pgr;”.
Furthermore, if PLL circuit is composed using above-mentioned phase comparator, it is necessary that the frequencies of the two input signals to the phase comparator are almost equal. As a result, a free degree of component of PLL circuit is greatly reduced. Furthermore, if a predetermined frequency is generated by a PLL circuit in which a divider is inserted in a loop, an output frequency is limited to integral times as much as frequency of reference signal.
In Japanese Patent Disclosure (Kokai) PH5-300014, a phase comparator applicable to the range of phase difference over “−2&pgr;~2&pgr;” is disclosed. However, in this phase comparator, a complicated analog circuit element, such as a reference signal generator of saw tooth signal or a differential phase generator of reference signal, is necessary. As a result, the circuit scale is very large and the cost greatly increases.
As mentioned-above, in the known phase comparator, a phase difference of two input signals whose frequencies are different is not detected. Especially, in case of composing a PLL circuit, it is necessary that frequencies of two input signals to the phase comparator are almost equal. As a result, the free degree of composition of PLL circuit becomes narrow, and a free degree of output frequency from PLL circuit is low.
Furthermore, in the phase comparator applicable to the case that the range of phase difference is over “−2&pgr;~2&pgr;” and frequencies of two input signals are different, the circuit scale becomes large and the cost becomes high.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a comparator able to detect a ratio of each frequency of two input signals whose frequencies are different, and to detect the phase difference of the two input signals whose frequencies are different using a simple digital circuit.
According to the present invention, there is provided a comparator for comparing a first binary input signal and a second binary input signal, comprising: a generator configured to generate a reset signal at each timing of a rising edge or a falling edge of the first input signal; and a counter configured to count the second input signal at each interval determined by the reset signal, the counted value represents a digital value representing a ratio of each frequency of the first input signal and the second input signal.
Further in accordance with the present invention, there is also provided a comparator for comparing a first binary input signal and a second binary input signal, comprising: a generator configured to generate a load signal at each rising edge or each falling edge of the input signal; and a counter configured to count the second input signal at each interval determined by the load signal, to calculate a difference between the counted value and a set value representing a predetermined ratio of each frequency of the first input signal and the second input signal, and to integrate the difference, the integrated value represents a phase difference of each frequency of the first input signal and the second input signal.
Further in accordance with the present invention, there is also provided a comparator for comparing a first binary input signal and a second binary input signal, comprising: a counter configured to count the second input signal at each timing of a rising edge or a falling edge of the first input signal; to calculate a difference between the counted value and a set value of integer part of predetermined ratio of each frequency of the first input signal and the second input signal, and to integrate the difference as a digital value; an integrator configured to integrate a set value of a decimal part of the predetermined ratio of each frequency of the first input signal and the second input signal; and a subtractor configured to calculate a difference between the digital value from said counter and the integrated value from said integrator, the difference represents a phase difference of each frequency of the first input signal and the second input signal.
Further in accordance with the present invention, there is also provided a comparator for comparing a first binary input signal and a second binary input signal, comprising: a counter configured to count the second input signal at each timing of a rising edge or a falling edge of the first input signal, and to output the counted value as a digital value representing a ratio of each frequency of the first input signal and the second input signal; a converter configured to convert a digital set value of non-integer digital set value as predetermined ratio of each frequency of the first input signal and the second input signal to a sequence of integer digital values whose average value coincides with the digital set value; and a subtractor configured to calculate a difference between the digital value output from said counter and integral digital values output from said converter.
Further in accordance with the present invention, there is also provided a comparator for comparing a first binary input signal and a second binary input signal, comprising: a converter configured to convert a digital set value of non-integer digital set value as predetermined ratio of each frequency of the first input signal and the second input signal to a sequence of integer digital values whose average value coincides with the digital set value; and a counter configured to count the second input signal at each timing of a rising edge or a falling edge of the first input signal, to calculate a difference between the counted value and the integral digital values, and to integrate the difference, the integrated value represents a phase difference of each frequency of the first input signal and the second input signal.
REFERENCES:
patent: 5835155 (1998-11-01), Jennes et al.
patent: 6169717 (2001-01-01), Kim et al.
patent: 5-300014 (1993-11-01), None
Kabushiki Kaisha Toshiba
Tran Khai
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