Compact single-poly two transistor EEPROM cell

Details Compact single-poly two transistor EEPROM cell Compact single-poly two transistor EEPROM cell

2000-08-22

2003-09-30

Fahmy, Jr., Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C365S185050, C365S185180

Reexamination Certificate

active

06627947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to electrically erasable programmable read only memory (“EEPROM”) cells.
2. Description of Related Art
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
The trend in construction of Electrically Erasable Programmable Read Only Memory (EEPROM) cells follows the general trend of semiconductor process technology in the move toward defining smaller device features. Conventional EEPROMs used “stacked gate” (or dual-poly) cells, wherein multiple applications of polysilicon formation were required to build cell structures. Recently, the conventional “stacked gate” EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, in EEPROM devices used for programmable logic devices, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
Conventionally, programmable logic EEPROMS were typically formed by stacked gate devices operating utilizing Fowler-Nordheim tunneling to program and erase the floating gate. Later, in an effort to improve process times and efficiency, single-layer polysilicon-based cells such as that set forth in U.S. Pat. No. 4,924,278, a schematic of which is shown in
FIG. 1
, were developed.
An EEPROM cell is typically made up of three separate transistors, namely, a write transistor, a sense transistor and a read transistor. The EEPROM cell is able to be programmed and erased by removing or adding electrons to a floating gate. Thus, in one example, the floating gate is programmed by removing free electrons from the floating gate and thereby giving the floating gate a positive charge. When it is desired to erase the EEPROM cell in this example, the floating gate is given a net negative charge by injecting electrons onto the floating gate. The read operation is performed by reading the state (current) of the sense transistor. In order to give the floating gate a positive charge (program) or negative charge (erase), electron tunneling, for example using the well-known Fowler-Nordheim tunneling technique, may be performed by applying the appropriate voltage potentials between the floating gate and a region, such as a drain region, of a transistor. Upon applying the appropriate voltage potentials, electron tunneling occurs through a tunnel oxide layer between the floating gate and the region.
As the feature sizes of EEPROM cells are scaled downward, the three-transistor EEPROM cells exhibit certain scaleablity, cost and reliability limitations. First, since three transistors (write, sense and read) form the typical EEPROM cell, the size of the EEPROM cell is large. Also, with a three-transistor cell, three oxide layers are needed that may vary in thicknesses requiring complex process steps to form the three tunnel oxide layers of varying thicknesses. Second, the manufacturing process for a smaller EEPROM cell becomes more complex and, accordingly, manufacturing costs rise as transistor channel lengths are reduced. For example, as the channel length of a transistor of the EEPROM cell is scaled downward, the thickness of the gate oxide overlying the channel must also be reduced since the gate oxide thickness must be scaled with the channel length. In view of the fact that EEPROM cells already have a complex process to form multiple oxide thicknesses, additional oxide thicknesses for the transistors would add additional steps to further complicate the manufacturing process and thereby increase manufacturing costs.
FIG. 1
shows a schematic diagram of one embodiment of the EEPROM structure shown in the '278 patent. The EEPROM structure disclosed therein utilizes a single layer of polycrystalline silicon and a control gate formed in the silicon substrate to eliminate the need to form a separate control gate and floating gate in two layers of polysilicon. The EEPROM structure is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to “program” the floating gate, a net positive charge is placed on the gate by removing free electrons from the floating gate. Likewise, to erase the floating gate, the floating gate is given a net negative charge by injecting electrons onto the floating gate.
An exemplary method of programming, erasing and writing to the cell in
FIG. 1
is given by Table 1:
TABLE 1
WL
BL
PT
PTG
Substrate
ACG
Read
V
cc
ground
V
sense
ground
ground
0
Program
V
pp
+
V
pp
ground
ground
ground
0
Erase
V
cc
ground
float
V
pp
ground
V
pp
+
This EEPROM structure has been well exploited in commercial devices. Nevertheless, as process technologies and practical considerations drive designers toward higher performance, alternative designs are investigated. The aforementioned cell structure requires, in a number of embodiments, a minimum oxide thickness of about 90-100 Å for the program junction oxide region due to the presence of the relatively high electric field across the oxide during the life of the cell. In order to accomplish scaling of the device, it would be desirable to provide a design wherein such region could be scaled without performance loss.
FIG. 2
shows an alternative single poly EEPROM cell wherein the cell designers strove to achieve a two-transistor cell. Nevertheless, a separate tunnel path, shown as a diode in
FIG. 2
, is required to remove electrons from the floating gate of the cell. This additional tunnel diode increases the overall size of the cell.
SUMMARY OF THE INVENTION
The invention, roughly described, comprises a non-volatile memory cell at least partially formed in a semiconductor substrate, comprising: a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.
In a further embodiment, the invention comprises a memory cell comprising: a first transistor having a gate coupled to a word line and a first active region in said substrate coupled to product term ground; a second transistor having a common floating gate, a second active region coupled to said first transistor and a third active region coupled to a product term voltage; an array control gate region in said substrate and capacitively coupled to said common floating gate via an oxynitride layer.


REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5594687 (1997-01-01), Lin
patent: 5969992 (1999-10-01), Mehta
patent: 5999449 (1999-12-01), Mehta
patent: 63-58959 (1988-03-01), None

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