Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-03-08
2005-03-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000
Reexamination Certificate
active
06864170
ABSTRACT:
A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor substrate and etching trenches in the first insulating layer. Metallic interconnects are formed in the trenches by metallization. The semiconductor structure is polished to remove metal from the first insulating layer, leaving behind metal in the trenches. A portion of the first insulating layer between the first and second metallic interconnects is etched so that the first and second metallic interconnects project above the first insulating layer. A second insulating layer is applied on the substrate such that the metallic interconnects project into the second insulating layer. The second insulating layer has a relative permittivity that is lower than the relative permittivity of the first insulating layer.
REFERENCES:
patent: 5747880 (1998-05-01), Havemann et al.
patent: 5751066 (1998-05-01), Havemann
patent: 5843845 (1998-12-01), Chung
patent: 6066577 (2000-05-01), Cooney, III et al.
patent: 6222269 (2001-04-01), Usami
patent: 6306754 (2001-10-01), Agarwal
patent: 6376911 (2002-04-01), Ryan et al.
patent: 6566241 (2003-05-01), Chun
patent: 43 19070 (1994-01-01), None
patent: 0 687004 (1995-12-01), None
patent: 0 759635 (1997-02-01), None
patent: 0 860880 (1998-08-01), None
patent: 11163523 (1999-06-01), None
patent: 11354638 (1999-12-01), None
patent: 2001 68548 (2001-03-01), None
Höhnsdorf Falko
Kieslich Albrecht
Weber Detlef
Fish & Richardson P.C.
Infineon - Technologies AG
Malsawma Lex H.
Smith Matthew
LandOfFree
Compact semiconductor structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Compact semiconductor structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact semiconductor structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3376870