Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1994-01-26
1995-01-03
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257304, 257390, 257311, 437 47, 437 52, 437 60, 365149, H01L 2968, H01L 2978
Patent
active
053789075
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor storage arrangement in a semiconductor substrate having storage cells, in each case consisting of a capacitor and an MOS selection transistor.
Semiconductor stores consist of a number of storage cells in a semiconductor substrate, consisting for example of silicon, which storage cells in each case comprise a capacitor for storing the information and a transistor for selecting the specific capacitor. In order to achieve a short access time and a small required area with a high memory capacity, the integration density of the arrangement must be increased, that is to say the space requirement of a cell must be minimized. However, it is not possible to reduce the size of all the structures of the cell in a linear manner since, for example, for reasons of electrical reliability the capacitor must not have less than a specific capacitance and structures of any desired fineness cannot be produced using the techniques which are available. Instead, a cell which is as small as possible for a given structure fineness must be achieved, that is to say the object is a cell which is as compact as possible. A measure for the extent to which a storage arrangement satisfies this object is the variable c:=cell area/(minimum structure size)2; c should thus be as small as possible.
If c is less than eight, the word lines and bit lines required to select a transistor then prevent further reduction of the size of the cell as long as only one cell is placed at each second crossing of a word line and bit line. This is the case in the so-called folded bit line scheme, which is used virtually without exception. In the case of values of c less than eight, it is necessary to place a cell at each crossing of a word line and bit line (so-called open bit line concept). However, with this wiring, it is not possible to carry out a comparative measurement of two adjacent bit lines during reading from a cell, as in the case of the folded bit line scheme, so that, in storage arrangements according to the open bit line concept, the assessment reliability of open bit line storage arrangements is in general less.
In order to produce a cell which is as small as possible, European reference 0,176,254, for example, discloses the capacitor being arranged in a trench in the semiconductor substrate, both electrodes of the capacitor being accommodated in the trench, in the form of conductive layers, and being insulated from the semiconductor substrate. Such a storage cell becomes even more compact as a result of a side wall contact which is proposed in U.S. Pat. No. 4,918,500: The connection of the first capacitor electrodes to a conductive region of the selection transistor is not made on the surface of the semiconductor substrate but on the trench wall, in that a layer which covers the trench wall and insulates the first electrode from the semiconductor substrate is removed at a point in the vicinity of the trench upper edge. Further designs for very-large-scale-integrated semiconductor storage arrangements are discussed in the article by N. Lu in the IEEE Circuits and Devices Magazine, January 1989, pages 27 to 36.
SUMMARY OF THE INVENTION
The object of the present invention is to specify a semiconductor storage arrangement which solves the aforementioned problems.
The present invention is a semiconductor storage arrangement having word lines, bit lines and storage cells in a semiconductor substrate. Each storage cell has a capacitor, which is arranged predominantly in a trench, and an MOS selection transistor. A vertical trench contact is arranged between a first conductive region of the selection transistor and a first electrode of the capacitor, at a first point on the trench wall. The bit line runs at least partially in the trench. A vertical bit line contact is arranged at a second point on the trench wall, between the bit line and a second conductive region of the selection transistor of the adjacent storage cell.
In a further development of the present invention a first
REFERENCES:
patent: 4894696 (1990-01-01), Takeda et al.
patent: 4912535 (1990-03-01), Okumura
patent: 4918500 (1990-04-01), Inuishi
"Advanced Cell Structures for Dynamic RAMs", Nicky C. C. Lu, IEEE Circuits and Devices Magazine, vol. 5, No. 1, Jan. 1989, pp. 27-26.
"A High Density 4Mbit d RAM Process Using a Fully Overlapping Bitline Contact (FoBIC) Trench Cell", K. H. Kusters et al, Siemens--Symposium on VLSI Technology, 1987, pp. 93-94.
Jackson Jerome
Monin, Jr. Donald L.
Siemens Aktiengesellschaft
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