Compact ROM matrix

Details Compact ROM matrix Compact ROM matrix

1997-06-02

1999-06-29

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257208, 257211, 438130, H01L 2976, H01L 2994

Patent

active

059172240

ABSTRACT:
A matrix memory array includes a P-type semiconductor substrate, thick oxide columns separating active columns, gate rows, a gate insulator interposed at the locations where these rows cover the active columns, N-type islands limited by the thick oxide columns and the gate rows, first conductive columns at the pitch of the active columns, constituting bit lines, second conductive columns at a pitch which is twice that of the first columns, constituting reference lines, and connections between each island and a first or second conductive column.

REFERENCES:
patent: 5241205 (1993-08-01), Shimizu et al.
patent: 5381030 (1995-01-01), Kasai
patent: 5442212 (1995-08-01), Eimori
patent: 5600171 (1997-02-01), Makihara et al.
Patent Abstracts of Japan, vol. No. 391 (E-0968), Aug. 23, 1990 & JP 02 144965 A (Hitachi Ltd), Jun. 4, 1990.
Copy of French Preliminary Search Report, Feb. 24, 1997.

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