Compact load-less static ternary CAM

Details Compact load-less static ternary CAM Compact load-less static ternary CAM

2000-11-28

2002-06-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S168000

Reexamination Certificate

active

06411538

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a ternary content addressable memory (TCAM), particularly to a TCAM that uses static random access memory (SRAM) cells.
BACKGROUND OF INVENTION
Many existing variants of TCAM use different combinations of SRAM storage cells and comparator structures. The storage node is usually one of the following: 4-T (with poly-load) SRAM cell, 6-T SRAM cell, or a dynamic random access memory (DRAM) cell. The comparator is usually a NAND or a pass-gate based XOR implementation.
Using a DRAM cell is not as fast as using a SRAM cell. Using a 6-T SRAM based storage cell makes the cell bigger than 4-T SRAM cell. Using a poly-load based 4-T SRAM cell is not easily scalable with technology.
SUMMARY OF INVENTION
The invention provides a TCAM wherein an individual TCAM cell uses two 1-bit 4-T SRAM storage cells. In so doing, the invention provides a TCAM that is more compact than a TCAM implementing 6-T SRAM cells. Also, by avoiding 4-T SRAM cells that incorporate load-resistive elements, the invention provides a TCAM that is scalable with technology.
Preferably, a TCAM cell of a TCAM system comprises two 1-bit 4-T SRAM data storage cells and a comparator. Taken together, these two 1-bit data storage cells provide any of three logic states (a logic 0, a logic 1 and a logic “Don't Care”) of the TCAM cell. The first 1-bit 4-T SRAM storage cell is coupled to a BL by a pass-gate PMOS transistor that has a NP drain diode section. A reverse-biased leakage current of this NP drain diode section is adapted to keep a dynamic node of the first SRAM storage cell high without relying on any resistive-load element. The second 1-bit 4-T SRAM cell is coupled to a another BL by a pass-gate PMOS transistor that has a NP drain diode section. A reverse-biased leakage current of this NP drain diode section is adapted to keep a dynamic node of the second SRAM storage cell high without relying on any resistive-load element. The comparator is coupled to these two 4-T SRAM storage cells. The comparator is adapted for matching a reference data with data communicated to the comparator from the two SRAM storage cells. Specifically, the comparator is a 4-T comparator coupled to these two 4-T SRAM storage cells, thereby making the TCAM a 12-T load-less static TCAM.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.


REFERENCES:
patent: 6262907 (2001-07-01), Lien et al.
patent: 6288922 (2001-09-01), Wong et al.

Affiliated with

Also associated with

Rating

Compact load-less static ternary CAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compact load-less static ternary CAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compact load-less static ternary CAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2961068