Compact ISA-bus interface

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

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Details

710126, 710 48, 710 58, 710260, G06F 1300, G06F 1338

Patent

active

060981415

ABSTRACT:
An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

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