Static information storage and retrieval – Read/write circuit – Data refresh
Patent
1988-04-14
1989-11-14
Gossage, Glenn A.
Static information storage and retrieval
Read/write circuit
Data refresh
365227, 365233, 365 45, 364707, 379 88, G11C 700, G11C 800, G06F 100
Patent
active
048812056
ABSTRACT:
A compact electronic apparatus employs a dynamic type memory, e.g., a dynamic random access memory (DRAM), a crystal oscillator circuit for generating a high frequency signal, and a resistor/capacitor (RC) circuit for generating a low frequency signal. When the apparatus is operated, the high frequency signal is used for accessing the data stored in the DRAM. When operation of the apparatus is interrupted, the DRAM is refreshed by the low frequency signal thus reducing the entire power consumption of the apparatus, since the power consumption of the RC oscillator circuit is lower than that of the crystal oscillator circuit.
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Casio Computer Co. Ltd.
Gossage Glenn A.
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