Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-20
2007-03-20
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10936202
ABSTRACT:
The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.
REFERENCES:
patent: 5359538 (1994-10-01), Hui et al.
patent: 6804811 (2004-10-01), Andreev et al.
patent: 6948145 (2005-09-01), Brown et al.
Andreev Alexander E.
Bolotov Anatoli
Pavisic Ivan
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