Compact contactless trenched flash memory cell

Details Compact contactless trenched flash memory cell Compact contactless trenched flash memory cell

1997-01-23

1998-08-18

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257318, 36518533, H01L 29788

Patent

active

057961417

ABSTRACT:
A compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

REFERENCES:
patent: 5075245 (1991-12-01), Woo et al.
patent: 5617351 (1997-04-01), Bertin et al.
"A Novel Memory Cell Using Flash Array Contactless EPROM (FACE) Technology," 1990 IEDM, pp. 90-94.
"A NAND Structured Cell With A New Programming Technology For Highly Reliable 5-V Only Flash EEPROM," 1990 Symposium on VLSI Technology, pp. 129-130.

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