Compact column redundancy CAM architecture for concurrent...

Details Compact column redundancy CAM architecture for concurrent... Compact column redundancy CAM architecture for concurrent...

2007-11-27

2007-11-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S049130

Reexamination Certificate

active

11266501

ABSTRACT:
A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The content addressable memory decodes the address and produces column redundancy information as an output. The column redundancy information is latched during a period complementary to the memory access cycle. By utilizing complementary memory access phases to latch memory addresses in contrast with a utilization of column redundancy information, a single set of registers may be used. Additionally, concurrent read and write operations are supported.

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