Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-29
2003-05-06
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S357000, C257S360000
Reexamination Certificate
active
06559507
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a NMOS structure and a method of limiting saturation current.
BACKGROUND OF THE INVENTION
A common way of protecting circuits against electrostatic discharge (ESD) is to use ESD protection clamps. In 80% to 90% of CMOS applications, grounded gate snapback N-MOS structures are the protection solution used. These work adequately during pulsed ESD operation but experience difficulties at continuous excessive currents or very high currents. The limited energy dissipation capabilities of grounded gate N-MOS ESD protection clamps can be attributed to the extremely localized region for heat dissipation, which corresponds to approximately a 0.5 &mgr;m region near the gate-drain region. Based on human body model (HBM) measurements, the peak critical power that can typically be handled by grounded gate N-MOS devices is no more than 50-100 mW per micron of contact width. Thus for a 6-8 V holding voltage, the current must not exceed 5-15 mA/&mgr;m.
A typical N-MOS snapback device includes a gate defined by a poly layer, a drain in the form of an n+ region and silicide (cobalt or titanium silicide) and a source. A plot of the IV characteristics of such a snapback device is illustrated in FIG.
1
and indicated by reference
10
. As is shown by the curve
10
, current increases virtually unchecked after triggering, and only tapers off at extreme currents due to increased resistance caused by heating. In order to avoid bum-out, it is important not only to limit the current, but also to avoid excessive local current densities. One prior art solution is to use separation resistance in the form of an un-silicided portion (ballast) between the gate and the silicided drain. The IV characteristics of such an un-silicided portion are shown by curve
12
in
FIG. 1
, which shows a clear saturation current curve. The combined effect of including a ballast region for the snapback N-MOS device is shown by curve
14
which, in many instances, will provide a current limit as indicated. However, since ESD protection structures are usually not created as designed specific devices, they have to meet a span of specifications. Thus, a long, space consuming, ballasting region is typically implemented of up to 6-10 &mgr;m. A plan view of such a prior art device is illustrated in
FIG. 2
in which the long n+ drain ballasting region is indicated by reference
20
. This long n+ ballasting region, which excludes silicide, acts like a saturation resistor for the N-MOS snapback structure. It will be appreciated that the space consuming ballast region significantly increases the size of the device. Furthermore, simply including a current limiting resistor may cause electrical current stratification or filamentation phenomenon. Such excessive localized current densities are generally observed for structures with negative differential conductivity. Also, in some processes (for example National Semiconductor's PVIP 50 NSC) do not provide sufficient current dumping to below mA/&mgr;m, even at 6 &mgr;m ballasting length. A numerical simulation study of the PVIP 50 NSC structure shows that even at 6 &mgr;m ballasting region length, the snapback saturation current is approximately 20 mA/&mgr;m, which exceeds the estimated physical limitation levels of 100 mW/&mgr;m since the corresponding current level limitation is 10 mA/&mgr;m. Thus it creates irreversible failure during ESD operation. Hence a new design and more specifically a new compact design for the drain ballasting region is needed for C-MOS protection structures.
The present invention provides for a reduced snapback saturation current in a NMOS device by proposing a solution that takes into account the structure and process associated with a typical N-MOS device.
FIG. 3
illustrates such a typical N-MOS device which includes a p-well or substrate
30
, and oxide layer
32
, and a polygate
34
. The drain region
36
and source region
38
are formed in the substrate
30
by introducing n dopants to define the drain and source
36
,
38
separated by a minimal gap
40
. The minimal dimension gap
40
which separates the two n+ regions
36
,
38
poses certain process difficulties due to the risk of dopant contamination. In order to avoid n dopant contamination in the space
40
when implanting the n+ regions of the drain and source, lightly doped regions
42
,
44
are first diffused into the well or substrate
30
, using the gate poly
34
as a mask. Thereafter, nitride spacers
46
are formed on either side of the gate poly
34
by depositing nitride over the entire structure and etching away the nitride to a certain depth. The high concentration n+ is then implanted. Typically, the high concentration n+ regions have doping levels that are approximately 100 times greater than the lightly doped regions. This process of first using lightly doped regions. This process of first using lightly doped regions is common in the art and, in the case of a drain, is typically referred to as a NLDD (lightly doped drain) region.
SUMMARY OF THE INVENTION
The present invention proposes using the NLDD region as a basis for achieving current limiting while avoiding excessive localized current densities.
Electrical currents stratification phenomenon, which is generally observed for any structure with negative differential conductivity, introduces problems. The present invention proposes defining distributed ballast drain regions to reduce current stratification through current spreading.
Also, since some processes such as PVIP 50 NSC do not achieve sufficient current dumping even at ballast lengths of 6 &mgr;m, the present invention proposes introducing a higher resistance level.
In accordance with the invention, there is provided a N-MOS snapback device with current limitation, which comprises a plurality of NLDD regions defined between a drain silicide and a gate of the device. The device typically includes a n+ drain ballasting region, wherein the NLDD regions may be formed in the n+ drain ballasting region of the device. Typically, the at least one NLDD region is larger than that of a conventional NMOS device, while the n+ composite region is smaller than that of a conventional NMOS device.
Further, according to the invention, there is provided a method of reducing snapback current in a snapback device by forming at least one distributed resistance means between gate and drain contacts of the device, for limiting saturation current, in addition to a n+ drain ballasting region. The distributed resistance means typically comprises at least one enlarged NLDD region which is ideally at least 1 &mgr;m in length.
Still further, according to the invention, there is provided a method of allowing the n+ drain ballasting region in a N-MOS snapback device to be reduced without substantially increasing current or localized current densities, by forming one or more NLDD regions in the current path between the drain silicide and the gate of the device. Preferably, the one or more NLDD regions are formed in the n+ drain ballasting region.
Still further according to the invention, there is provided a method of limiting snapback current in a N-MOS device, comprising forming at least one NLDD blocking regions between a drain silicide of the device and a gate of the device, wherein the majority of the length of the at least one NLDD region extends past the edge of the gate towards the drain contact. The device may further include a n+ drain ballasting region which may be formed between the drain silicide and the NLDD blocking region or may be distributed with the one or more NLDD blocking regions disbursed in the n+ drain ballasting region.
Still further, according to the invention, there is provided a NMOS snapback device, comprising at least one NLDD region defined between a drain contact and a gate of the device, wherein the majority of the length of the at least one NLDD region extends past the edge of the gate towards the drain contact. Typically the NLDD region is
Strachan Andy
Vashchenko Vladislav
Flynn Nathan J.
Mondt Johannes P
National Semiconductor Corporation
Vollrath & Associates
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