Compact and highly efficient DRAM cell

Details Compact and highly efficient DRAM cell Compact and highly efficient DRAM cell

2005-06-14

2005-06-14

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S185260, C365S206000

Reexamination Certificate

active

06906946

ABSTRACT:
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

REFERENCES:
patent: 5293212 (1994-03-01), Yamamoto et al.
patent: 5623442 (1997-04-01), Gotou et al.
patent: 5646060 (1997-07-01), Chang et al.
patent: 6778419 (2004-08-01), Barry et al.

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