Compact and fast row driver/decoder for semiconductor memory

Details Compact and fast row driver/decoder for semiconductor memory Compact and fast row driver/decoder for semiconductor memory

1994-12-23

1996-07-09

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326108, 36523006, 365203, H03K 19017

Patent

active

055347975

ABSTRACT:
The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits. The signal generating circuit output maintains the gate voltage of each of the input transistors near the edge of conduction when receiving the signal that the voltage of the respective row line is to be raised. Otherwise the signal generating circuit maintains the gate voltage at ground potential.

REFERENCES:
patent: 4618784 (1986-10-01), Chappell
patent: 4788457 (1988-11-01), Mashiko
patent: 4827160 (1989-05-01), Okano
patent: 5018107 (1991-05-01), Yoshida

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