Communications system with multiple, simultaneous accesses to a

Details Communications system with multiple, simultaneous accesses to a Communications system with multiple, simultaneous accesses to a

1997-12-01

1999-02-16

Shah, Alpesh M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395311, 3952003, 711168, G06F 1300

Patent

active

058729933

ABSTRACT:
The present invention comprises an architecture that involves an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a microcontroller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

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