Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
1998-10-13
2001-02-13
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C710S010000, C710S009000, C710S008000, C710S116000
Reexamination Certificate
active
06189059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a communications system that has at least one slave station and one master station to control it. The slave stations cannot operate without the master station.
A communications system can be realized, for example, by the Inter IC (I
2
C) bus. A plurality of master stations and a plurality of slave stations are connected to the I
2
C bus via open-collector outputs. The master stations control the slave stations using addresses which are known to them and which are permanently stored in the slave stations.
It is possible, in the case of the I
2
C bus, for two master stations simultaneously to attempt to access the bus in order to address slave stations. For this case, a so-called arbitration procedure is provided for the I
2
C bus. In this procedure, the competing master stations simultaneously transmit bit by bit in each case one individual identification code, stored in them, onto a pre-charged line of the bus via their open-collector outputs. The potential of the line is drawn to earth as soon as one of the bits which is about to be output has a high level, even if the bit of the other master station has a low level. Each of the master stations monitors whether that bit of its identification code which has just been output has a high level when the line is being discharged. If this is not the case, the master station deactivates itself and that master station whose identification code with all its bits is decisive for the successive potential states of the line manages to access the bus.
A host computer which assigns new addresses to peripheral units is described in British Patent Application GB 2 217 561 A. Here, the peripheral units simultaneously output on a bit-by-bit basis, identification numbers which are stored in them and, in doing so, carry out a collision detection. Only one of the peripheral units ultimately comes through while the others are deactivated owing to the collision detection. Subsequently, the host transmits a new address to the last peripheral unit that is still active and the unit stores the address. The unit can subsequently be addressed by the new stored address.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a communications system with a master station and at least one slave station, which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which it is possible to connect any desired number of slave stations whose addresses and whose number are not known beforehand to the master station controlling them, and in which the transfer of a new address from the master station to the particular slave station is dispensed with.
With the foregoing and other objects in view there is provided, in accordance with the invention, a communications system, including: a line; a plurality of slave stations each storing an identification code formed of bits carrying one of two logic states, each of the plurality of slave stations having a first output circuit with an output terminal connected to the line, the identification code of each of the plurality of slave stations being transmitted simultaneously bit by bit to the line via a respective first output circuit, if a first logic state is simultaneously present at all of the first output circuits the line assumes a first potential, if a second logic state is present at one of the first output circuits the line assumes a second potential, the plurality of slave stations each having a monitoring means monitoring if a respectively read-out bit of a respective identification code has the second logic state in the event that the line assumes the second potential and the monitoring means deactivating a respective slave station if the respective read-out bit has the first logic state; and a master station controlling the plurality of slave stations, the master station having a master monitoring means for monitoring a potential of the line during the transmittal of the identification codes by the plurality of slave stations for registering the identification code of a last active slave station, the master station having a memory receiving and storing the identification codes so that a corresponding slave station can subsequently be addressed by the master station by the respective identification code stored in the master station.
With the foregoing and other objects in view there is also provided, in accordance with the invention, in combination with a communications system having at least one slave station and a line, a master station connected to the line and controlling an operation of the at least one slave station in the communications system, including: an address-generating means determining a potential of the line and assigning addresses to the at least one slave station, the address-generating means storing as one of the addresses each chronologically successive potential state of the line.
Whereas, in the case of the I
2
C bus, an identification code is stored in each master station. According to the invention there is provision for an identification code to be stored in each slave station. The identification code is different for each slave station and can have a multiplicity of bits.
Whereas, in the case of the I
20
C bus, an access authorization of competing master stations to the bus is determined by outputting their identification codes, in the case of the invention a similar procedure is used to identify any desired number of unknown slave stations by a master station. Identification is understood here to be the detection of connected slave stations and the assignment of addresses to the slave stations by the master station.
In the case of the communications system according to the invention, the master station can detect how many slave stations that have previously been unknown to it (that is to say do not have any assigned address) are connected to the system. The master station assigning to each of the slave stations an address via which it can then be addressed. The number of slave stations connected to the system is irrelevant for this.
The number of slave stations is determined by carrying out the identification according to the invention. When there is a new identification cycle (starting with the outputting of the first bit of the identification codes) the identification continues until no more slave stations signal, by outputting their identification code, that they have not yet been identified. This is the case if an address has been assigned to all the slave stations connected to the communications system and the slave stations have then been deactivated. If this case arises, the master station terminates the identification procedure.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a communications system with a master station and at least one slave station, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4463445 (1984-07-01), Grimes
patent: 5226123 (1993-07-01), Vockenhuber
patent: 5361005 (1994-11-01), Slattery et al.
patent: 5499242 (1996-03-01), Lee et al.
patent: 5524269 (1996-06-01), Hamilton et al.
patent: 5787306 (1998-07-01), Michael
patent: 5805817 (1998-09-01), Yu et al.
patent: 6003097 (1999-12-01), Richman et al.
patent: 0 051 332 B1 (1982-05-01), None
patent: 0 221 303 A2 (1987-05-01), None
patent: 2 217 561 (1989-11-01), None
Born Christine
Endriss Heinz
Gossmann Timo
Mehrgardt Sonke
Sotek Karel
Greenberg Laurence A.
Infineon - Technologies AG
Lee Thomas C.
Lerner Herbert L.
Peyton Tammara
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