Communications interface adapter for a computer system including

Details Communications interface adapter for a computer system including Communications interface adapter for a computer system including

1998-06-02

2000-07-04

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt queuing

710266, 710 22, G06F 948, G06F 1314, G06F 1324

Patent

active

06085278&

ABSTRACT:
To facilitate access of interrupt status information, interrupt posting status. POST.sub.-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST.sub.-- STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST.sub.-- STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST.sub.-- STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST.sub.-- STAT registers. A host system software driver accesses the interrupt posting status POST.sub.-- STAT registers via a bus access operation, changes a bit in a POST.sub.-- STAT register, and monitors the result of the access and bit change in the mirror of the POST.sub.-- STAT register in the system memory without a further bus read access. Advantageously, multiple accesses through the bus to verify when the written value status is correct is eliminated.

REFERENCES:
patent: 4326247 (1982-04-01), Chamberlin
patent: 5131081 (1992-07-01), MacKenna et al.
patent: 5666559 (1997-09-01), Wisor et al.
patent: 5689726 (1997-11-01), Lin
patent: 5819112 (1998-10-01), Kusters

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