Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-20
2009-06-09
Pham, Chi H. (Department: 2416)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07546570
ABSTRACT:
A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.
REFERENCES:
patent: 4621201 (1986-11-01), Amdahl et al.
patent: 5266833 (1993-11-01), Capps
patent: 5625563 (1997-04-01), Rostoker et al.
patent: 6858356 (2005-02-01), Savaria et al.
patent: 6928606 (2005-08-01), Savaria et al.
Blaquiere Yves
Norman Richard S.
Savaria Yvon
Hyperchip Inc.
Hyun Soon D.
Ogilvy Renault LLP
Pham Chi H.
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