Communication systems, circuits, circuit systems and methods...

Details Communication systems, circuits, circuit systems and methods... Communication systems, circuits, circuit systems and methods...

1999-03-22

2003-02-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S724000

Reexamination Certificate

active

06519724

ABSTRACT:

TECHNICAL FIELD
The present invention relates to communication systems, circuits, circuit systems and methods of operating a circuit.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a prior art circuit
10
is illustrated. The depicted circuit
10
includes combinational logic circuitry
12
coupled with a plurality of flip-flops
14
. The depicted flip-flops comprise D-type flip-flops. The illustrated flip-flops
14
are configured to receive signals from combinational logic circuitry
12
via a D input and output signals to combinational logic circuitry
12
using a Q output. A common clock signal is applied to a clock (CK) input of the individual flip-flops
14
to provide a common timing reference.
The three left-most flip-flops
14
of
FIG. 1
include reset inputs. Combinational logic circuitry
12
can provide reset control signals to selectively reset the three left-most flip-flops
14
. Typically, combinational logic circuitry
12
applies a logical high reset control signal to the reset inputs of the three left-most flip-flops
14
. Such reset control signals may be selectively strobed to a logic low state to reset the corresponding flip-flops
14
.
Referring to
FIG. 2
, another conventional circuit configuration
30
is illustrated. Circuit
30
includes combinational logic circuitry
32
coupled with plural scan flip-flops
20
. In the illustrated configuration, scan flip-flops
20
are arranged in a shift register configuration. Individual scan flip-flops
20
are coupled with combinational logic circuitry
32
.
OR gates
34
are coupled with respective reset inputs of scan flip-flops
20
. The inputs of respective OR gates
34
are coupled with combinational logic circuitry
32
and a test mode (“TESTMODE”) signal control line. During testing of circuitry
30
, an external test circuit (not shown) holds the TESTMODE signal in a logical high state. Accordingly, control signals applied from respective OR gates
34
to corresponding reset inputs of scan flip-flops
20
are also in a logical high state.
Such a circuit configuration introduces untestable logic circuitry within combinational logic circuitry
32
. In particular, the corresponding circuitry within combinational logic circuitry
32
utilized to drive the input signals into respective OR gates
34
typically cannot be monitored during test mode operations of conventional circuit
30
inasmuch as the TESTMODE signal is by definition in a logical high state.
Referring td
FIG. 3
, a timing diagram corresponding to operations of conventional circuit
30
is depicted. Time in the illustrated diagram progresses from left to right. Line
36
illustrates the operation of the clock signal applied to scan flip-flops
20
. In addition, the clock signal may be also applied to combinational logic circuitry
32
to provide a common timing reference.
Line
37
illustrates an ideal reset (“IDEALRESETn”) signal generated within combinational logic circuitry
32
to be applied to a corresponding OR gate
34
. The IDEALRESETn signal is generated to control the reset input of the corresponding scan flip-flop
20
. Line
38
represents a real reset (“REALRESETn”) signal which is typically actually outputted and applied to OR gates
34
. More specifically, during operation in a test mode with the utilization of test vectors, it is possible to have parasitic pulses as represented at pulse
39
due to race conditions. Accordingly, during test mode operations, the TESTMODE signal in utilized to hold the output of OR gates
34
in a logical high state to avoid the generation of parasitic pulses and the unwanted resetting of scan flip-flops
20
.
Line
40
represents the output of OR gates
34
comprising a reset test (“RESETnTEST”) signal during the test mode operations. As depicted, the RESETnTEST signal applied to a respective reset input of a corresponding scan flip-flop
20
is held in a logical high state responsive to the assertion of the TESTMODE signal. Such avoids the generation of parasitic pulses, but also has the disadvantage of adding untestable faults. More specifically, the circuitry within combinational logic circuitry
32
which outputs the REALRESETn signal to OR circuitry
34
is untestable during testing operations.
Accordingly, there exists a need to provide improved circuitry and methods for implementing testing operations.


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Gibson, Jerry D.The Communications Handbook. pp. 1305-1326, CRC Press 1997.

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