Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2007-03-20
2009-12-08
Myers, Paul R (Department: 2111)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C710S110000
Reexamination Certificate
active
07631212
ABSTRACT:
A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.
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Safe—by—Wire—Plus Version 2.0 Sep. 24, 2004.
Ishihara Hideaki
Matsuoka Toshihiko
Misawa Katsutoyo
Rinnai Masato
DENSO CORPORATION
Myers Paul R
Posz Law Group , PLC
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