Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
1998-11-02
2002-04-16
Beausoleil, Robert (Department: 2781)
Electrical computers and digital data processing systems: input/
Input/output data processing
C370S428000, C370S503000, C379S039000, C379S219000
Reexamination Certificate
active
06374309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a communication signal suppressing apparatus and a common line signal apparatus employed in, for instance, the No. 7 common line signal system. More specifically, the present invention is directed to such a communication signal suppressing apparatus and a common line signal apparatus capable of reducing workloads given to firmware.
2. Description of the Related Art
Common line signal apparatuses used in the No. 7 common line signal system are realized by utilizing not only hardware, but also firmware (software), as well known in this field. Concretely speaking, an apparatus portion of such a common line signal apparatus in which a simple (regular) process operation, e.g., “0” insertion/deletion and CRC check is performed is realized by hardware (LSI), whereas another apparatus portion thereof in which an abnormal condition of a received number and so on can be solved is realized by using firmware.
In general, it is preferable to reduce workloads given to firmware sides (CPU sides) of appliances operable with firmware. This load reducing technique is similarly applied to common line signal apparatuses in order to reduce workloads given to firmware sides thereof. For example, in the case of the No. 7 common line signal system, there are possibilities that frames having the same contents (FISU: Fill in Signal Unit) which own merely meaning of a confirmation response are received many times, due to protocol characteristics. To avoid that such useless frames are transferred to the firmware sides, in the case that FISUs having the same contents are continuously received in the presently available common line signal apparatus, the following suppressing hardware is employed. That is, this suppressing hardware can suppress the FISUs having the same contents subsequent to the second (or third) FISU, namely the hardware can discard the same FISUs without transferring these same FISUs to the firmware side.
However, when the common line signal apparatus is arranged in order to reduce product cost thereof, by which a plurality of channels can be accepted, the random occurrence possibilities of FISUs are increased. As a result, there is such a problem that the workload given to the firmware side cannot be reduced by the above-explained suppressing function.
Therefore, the present invention has been made to solve the above-described problem, and has an object to provide a communication signal suppressing apparatus capable of reducing a workload given to a firmware-operated portion of this communication signal suppressing apparatus while a communication signal apparatus typically known as a common line signal apparatus is constituted.
Another object of the present invention is to provide a common line signal apparatus capable of reducing a workload given to a firmware-operated portion thereof.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a communication signal suppressing apparatus operatively connected to a processing apparatus whose operation sequence is determined based upon firmware so as to constitute a communication signal apparatus is comprised of: storage means for storing therein both a minimum value of an expected value of a reverse-direction sequence number and a maximum value thereof, the processing apparatus being capable of accessing the storage means; rewriting means for rewriting the minimum value stored in the storage means based upon a reverse-direction sequence number of a received frame in such a case that the reverse-direction sequence number of the received frame is present within a range defined by the minimum value and the maximum value stored in the storage means, and furthermore, a reverse-direction state indication bit of the received frame, a forward-direction state indication bit thereof, and a forward-direction sequence number thereof are made coincident with a reverse-direction state indication bit of a previously received frame, a forward-direction state indication bit thereof, and a forward-direction sequence number thereof, respectively; and frame output means for discarding the frame which has been used to rewrite the minimum value stored in the storage means by the rewriting means, and for outputting a content of a frame which has not been used to rewrite the minimum value to the processing apparatus.
In other words, the communication signal suppressing apparatus of the present invention does not discard the frames having the same contents, but owns the following function. That is, a frame having only meaning of a confirmation response is discarded, and the latest value of the reverse-direction sequence number of the discarded frame is stored in the storage means. Accordingly, in such a case that a communication signal apparatus such as a common line signal apparatus is constituted by using the communication signal suppressing apparatus of the present invention, the processing apparatus operatively connected to this circuit can acquire the reverse-direction sequence numbers at arbitrary timing in a batch mode without checking the contents thereof every time the confirmation response is received. The reverse-direction sequence numbers correspond to such information required to confirm that the transmitted frame is actually delivered to the communication party. This processing apparatus is constructed of a CPU, a ROM for storing thereinto firmware used to define an operation sequence thereof, a RAM for temporarily saving data given by the frame, and so on. As a consequence, when this communication signal suppressing apparatus is employed, the workload given to the processing apparatus with employment of the firmware can be reduced, and also such a communication signal apparatus capable of storing a plurality of channels can be simply realized.
It should be understood that when this communication signal suppressing apparatus is arranged by holding only the reverse-direction sequence numbers of the discarded frames, the processing apparatus cannot recognize the number of frames discarded by this circuit. As a consequence, when a communication signal suppressing apparatus is arranged in accordance with the present invention, it is preferable to additionally provide such a counting means for counting a total number of received frames, depending on sorts of these received frames.
Alternatively, a communication signal suppressing apparatus according to the present invention may be arranged in such a manner that this communication signal suppressing apparatus can be operatively connected to the existing communication signal apparatus. In other words, the communication signal suppressing apparatus according to the present invention may be arranged as an externally equipped circuit of a communication signal apparatus. This communication signal suppressing apparatus may suppress such a frame having only meaning of a confirmation response, among the entered frames.
In accordance with the present invention, since the amount of data to be processed by the firmware can be reduced, for instance, a common line signal apparatus for accepting multiple channels can be simply realized at a low cost.
REFERENCES:
patent: 5757895 (1998-05-01), Aridas et al.
patent: 5892812 (1999-04-01), Pester, III
patent: 6219416 (2001-04-01), Benayoun et al.
patent: 63-9338 (1988-01-01), None
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patent: 3-21153 (1991-01-01), None
Kazehaya Kenji
Morita Sumie
Ouchi Hitoshi
Shibata Megumi
Yoda Hiroyoshi
Beausoleil Robert
Chung-Trans X.
Fujitsu Limited
Rosenman & Colin LLP
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