Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-06-17
2001-03-06
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S106000, C710S116000
Reexamination Certificate
active
06199132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to data communication via busses and more particularly to optimizing a bus for personal computer data traffic.
2. Description of the Related Art
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to peripherals or bulk data transmissions from a hard drive into system memory.
At present, proper support for both kinds of data in computer systems is inadequate. For example, the peripheral component interface (PCI) bus, a major input/output bus in present computer architectures, does not support isochronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data become unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance. Thus, there exists a need to appropriately accommodate both kinds of data in present and future computer systems.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method and apparatus which guarantees isochronous data a specified amount of bandwidth and worst-case latency. Further, the bus protocol attempts to reduce latency for transfer of asynchronous data in order to improve system performance. At the beginning of a bus frame, the bus transfers data in asynchronous priority mode by prioritizing transfer of asynchronous data over isochronous data. According to the bus protocol, each bus interface tracks the amount of isochronous data transmitted and the bus switches to isochronous priority mode if necessary to guarantee isochronous bandwidth for the frame. If the bus switches to isochronous priority mode, the bus stays in isochronous priority mode until all isochronous transfers are complete.
In a first embodiment, the invention provides a method of transferring information on a bus between a first and a second integrated circuit, the information includes address information, isochronous data, asynchronous data and control information. The method includes transferring data on the bus in asynchronous priority mode during a first portion of a first time period, wherein asynchronous data is transferred preferentially over isochronous data. Transfers over the bus selectably switch to isochronous priority mode for a second portion of the first time period to guarantee transfer of a predetermined amount of isochronous data during the first time period.
In another embodiment, the invention provides an apparatus including a bus interface coupled to transfer information to and from a bus, the information including address information, isochronous data, asynchronous data and control information. The bus interface includes an arbiter circuit responsive to a priority mode of the bus to selectably transfer either asynchronous or isochronous data over the bus. The arbiter circuit also determines a priority mode of the bus, the priority mode being asynchronous priority mode during a first portion of a first time period on the bus. The arbiter circuit guarantees transfer of a predetermined amount of isochronous data by selectably switching to asynchronous priority mode for a second portion of the first time period.
REFERENCES:
patent: 5422883 (1995-06-01), Hauris et al.
patent: 5450411 (1995-09-01), Heil
patent: 5621898 (1997-04-01), Wooten
patent: 5640392 (1997-06-01), Hayashi
patent: 5742847 (1998-04-01), Knoll et al.
patent: 5758075 (1998-05-01), Graziano et al.
patent: 5758105 (1998-05-01), Kelley et al.
patent: 5761430 (1998-06-01), Gross et al.
patent: 5761448 (1998-06-01), Adamson et al.
patent: 5872998 (1999-02-01), Chee
patent: 5948080 (1999-09-01), Baker
patent: 6011784 (2000-01-01), Brown et al.
Intel Corporation, “Accelerated Graphics Port Interface Specification”, Revision 1.0, Jul. 31, 1996, pp. 1-152.
Wickelgren, Ingred J., “The Facts About Fire Wire”, IEEE Spectrum, Apr. 1997, pp. 20-25.
Gwennap, Linley, “MediaGX Targets Low-Cost PCs”, Microprocessor Report, vol. 11, No. 3, Mar. 10, 1997, pp. 1-6.
Compaq, Digital Equipment Corp., IBM PC Company, Intel, Microsoft, NEC, and Northern Telcom, “Universal Serial Bus Specification”, Revision 1.0, Jan. 15, 1996, pp. 3-268, particularly Chapters 4 and 5.
Gulick Dale E.
Hewitt Larry D.
Advanced Micro Devices , Inc.
An Meng-Ai T.
Monestime Mackly
Zagorin O'Brien & Graham LLP
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