Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-04-07
2003-12-16
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S105000, C710S305000
Reexamination Certificate
active
06665757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication Interface between a single system serving as a master (hereinafter, referred to as a “master system”) and a plurality of systems serving as slaves (hereinafter, referred to as “slave systems”).
2. Description of the Related Art
Various communication interfaces have been proposed and standardized in the art for communicating a plurality of systems with one another. Examples of such conventional communication interfaces used between a master system and one or more slave systems will now be described.
As a first conventional example, a conventional PC card ATA I/O mode interface will be described below.
FIG. 13
illustrates signal lines included in a conventional PC card ATA I/O mode interface. Referring to
FIG. 13
, the conventional PC card ATA I/O mode interface includes: signal lines
101
(“A
00
”-“A
10
”) through which an address is input by designating one of addresses A
00
-A
10
in a slave system to be accessed by a master system; data input/output signal lines
102
(“D
00
”-“D
15
”) for data/command/status information; a signal line
103
(“-CE”) through which the master system selects one of a plurality of slave systems: a signal line
105
(“-IREQ”) through which the master system is notified of the internal operation state of the slave system: a write control signal line
106
(“-IOWR”) through which the master system controls outputs from the master system to the signal lines
102
and inputs to the slave system; and a read control signal line
107
(“-IORD”) through which the master system controls outputs from the slave system to the signal lines
102
and inputs to the master system.
A basic operation, i.e., a read/write operation, of a conventional communication system including these signal lines connected between the master system and the slave systems will now be described.
Each of
FIGS. 14A and 14B
is a timing diagram illustrating a communication protocol for use in the conventional PC card ATA I/O mode interface.
FIG. 14A
illustrates a conventional method by which the signal lines are operated when the master system reads data from a slave system. The master system controls the slave system selection signal line
103
to go low so as to select one of the slave systems with which the master system is to communicate. Then, the master system transmits a register address in the slave system at which a read address is to be stored and the read address to the address signal lines
101
and the data input/output signal lines
102
, respectively. At the same time, the master system controls the write control signal line
106
, through which inputs to the slave system are controlled, to go low. The write control signal line
106
is kept low for a predetermined period and is then controlled to go high, thereby setting the address register in the slave system, which indicates the address from which data is to be read out. The address of the data to be read out is designated by repeating this operation of setting the address register in the slave system using the address signal lines
101
, the data input/output signal lines
102
and the write control signal line
106
. Then, the register address in the slave system for storing the command address and prescribed data, which indicates a read command, is transmitted to the address signal lines
101
and the data input/output signal lines
102
, respectively, in order to issue a read command to the slave system. At the same time, the write control signal line
106
, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high, whereby the slave system interprets the data received from the data input/output signal lines
102
in order to determine whether a read request has been issued from the master system, thereby starting to read data from a memory device in the slave system. Thereafter, when the read data is ready, the slave system controls the signal line
105
, which indicates the internal state of the slave system, to go low. The master system detects the high-to-low transition of the signal line
105
, which indicates the internal state of the slave system, after which the master system transmits the address of the status register of the slave system to the address signal lines
101
. At the same time, the master system controls the read control signal line
107
, through which outputs from the slave system are controlled, to go low. The master system keeps the read control signal line
107
low for a predetermined period and then controls the read control signal line
107
to go high, thereby receiving the status of the slave system through the data input/output signal lines
102
. Thereafter, the master system transmits the address of the data register of the slave system to the address signal lines
101
. At the same time, the master system controls the read control signal line
107
, through which outputs from the slave system are controlled, to go low. The master system keeps the read control signal line
107
low for a predetermined period and then controls the read control signal line
107
to go high. Thus, the operation of receiving the read data through the data input/output signal lines
102
is repeated so that the master system receives data having a particular data length from the slave system.
FIG. 14B
illustrates a conventional method by which the signal lines are operated when the master system writes data to a slave system. Setting of an address register which indicates the address at which data is to be written is performed by a manner similar to that illustrated in FIG.
14
A. Then, the register address in the slave system for storing the command address and prescribed data which Indicates a write command is transmitted to the address signal lines
101
and the data input/output signal lines
102
respectively, in order to issue a write command to the slave system. At the same time, the write control signal line
106
, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high, whereby the slave system interprets the data received from the data input/output signal lines
102
in order to determine whether a write request has been issued from the master system, and the slave system waits for write data. Then, the master system transmits the address of the data register of the slave system to the address signal lines
101
. At the same time, the write control signal line
106
, through which inputs to the slave system are controlled, is kept low for a predetermined period and is then controlled to go high. Thus, the operation of transmitting the write data through the data input/output signal lines
102
is repeated so that the master system transmits data having a particular data length to the slave system. When the transmission is complete, the slave system writes write data in a memory device in the slave system. When the write operation is complete, the signal line
105
, which indicates the internal state of the slave system, is controlled to go low. The master system detects the high-to-low transition of the signal line
105
, which indicates the internal state of the slave system, after which the master system transmits the address of the status register of the slate system to the address signal lines
101
. At the same time the master system controls the read control signal line
107
, through which output from the slave system are controlled to go low. The master system keeps the read control signal line
107
low for a predetermined period and then controls the read control signal line
107
to go high, thereby receiving the status of the slave system through the date input/output signal lines
102
in order to confirm completion of the operation.
As a second conventional example, a conventional microcontroller interface will be described below.
FIG. 15
illustrates signal lines Included in a conventional microcontroller interface. Referrin
Fujii Masaru
Hosokawa Tatsuhiro
Kawai Hideki
Sakurai Hiroshi
Sekibe Tsutomu
Matsushita Electric - Industrial Co., Ltd.
Park Ilwoo
Snell & Wilmer LLP
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