Communication device

Details Communication device Communication device

2008-04-15

2008-04-15

Corrielus, Jean B. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S291000

Reexamination Certificate

active

10862320

ABSTRACT:
In a communication device, a counter counts a reference clock CLK1at each edge of a data signal, and a clock generator generates a reception clock corresponding to the count value of the counter. When there is a frequency lag between the reception clock and the frequency of the transmission clock at a communication partner side, the count value when an edge detection signal is at a H-level is deviated from the count value. This deviation reflects decode signals DS1to DS3, and phase delay or phase advance is detected on the basis of a signal P1or P2. At this time, the estimated value of the next edge period is increased/reduced by only “1”. When the deviation of the count value occurs sequentially, a frequency excessively-small state or excessively-large state is detected on the basis of the signal F1or F2. At this time, the estimated count value of the next edge period is increased/reduced by only “2”.

REFERENCES:
patent: 5787132 (1998-07-01), Kishigami et al.
patent: 6643346 (2003-11-01), Pedrotti et al.
patent: 2004/0071251 (2004-04-01), Sutioso et al.
patent: B-2-17080 (1990-04-01), None

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