Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-05-01
2003-05-13
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C710S104000, C710S317000, C710S052000, C370S402000
Reexamination Certificate
active
06564280
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of data communications and more particularly to dynamically configuring bus master engines and other hardware resources to effectively use these hardware resources for various peripheral bus functions.
DESCRIPTION OF THE RELATED ART
Data may be communicated across a transmission medium at different rates and using different protocols. For example, a conventional voice-band modem can connect computer users through a Public Switched Telephone Network (PSTN). The data transmission rate of a voice-band modem is typically 56 kilobits/second (Kbps). As consumer demand for interactive electronic access to entertainment (e.g. video-on-demand) and information (e.g. Internet) in digital format has increased, this demand has exceeded the capabilities of conventional voice-band modems. Consequently, new technologies have been developed to transmit data at a faster rate.
One such technology allows relatively high-speed data transmission over existing copper-based twisted-pair lines connecting a home to the telephone company central office. This technology, referred to as digital subscriber line (DSL) technology, includes various species, including high-bit-rate DSL (HDSL), very high-bit-rate (VDSL), and asymmetric DSL (ADSL). These different types of digital subscriber line technologies are generically referred to as “xDSL” technologies. Each of these technologies allows digital information to be transmitted from a service provider over existing copper telephone lines at rates as high as 6 megabits/second (Mbps).
Computer systems may consequently receive data that has been transmitted at different rates and using different protocols. In order to accommodate these different communication standards, computer systems may be configured to implement a communication medium interface for each type of data rate and protocol. A communication medium interface may include a codec (coder/decoder). A codec may include an A/D converter, a D/A converter and a serial interface for a respective data rate and protocol.
The A/D converter of a communication medium interface receives analog samples of the data being transmitted across the transmission medium and converts these samples into digital data. The digital data is then stored in a buffer. A bus master engine then generates a request to become master of a peripheral bus, such as a Peripheral Component Interconnect (PCI) bus. Once the bus arbiter grants the request of the bus master engine, the bus master engine then transfers the contents of the buffer into a host memory. The host processor then processes the samples.
In contrast, when the host desires to output communication data, the host processor may create output samples and place them in the host memory. When the PCI bus arbiter grants the request of the bus master engine to become master of the PCI bus, the bus master engine transfers these output samples into a buffer. These output samples may then be converted into analog signals by the D/A converter of the communication medium interface before being transmitted across the transmission medium.
A PCI function, e.g., voice-band modem, DSL modem, LAN, etc., may be typically associated with a set of a bus master engine, a buffer and a communication medium interface. For example, a particular communication medium interface may be configured to receive data at a rate of 56 kbps (voice-band modem). Once the A/D converter in the communication medium interface receives analog data, a digitized version of this analog data may only be stored in the buffer associated with that particular PCI function, i.e., the voice-band modem. Furthermore, a bus master engine associated with that particular PCI function, i.e., the voice-band modem, transfers the contents of the buffer associated with the voice-band modem into a host memory upon granting of the request from the PCI arbiter.
Unfortunately, the above-described configuration is not flexible across a variety of communication medium interfaces. For example, when a plurality of telecommunication standards are supported, a plurality of sets of bus master engines, buffers and communication medium interfaces are required in prior art systems. In addition, in prior art systems, components used by different telecommunication standards cannot be shared. This may result in a duplication of hardware resources, which is an unnecessary expense.
It would therefore be desirable that a set or subset of bus master engine(s), buffer(s) and communication medium interface(s) can be used in multiple peripheral bus function(s) that do not operate simultaneously. It would further be desirable that a plurality of individual components be aggregated together with other components to perform a single peripheral bus function, e.g., a plurality of buffers be used together with at least one bus master engine and at least one communication medium interface to perform a single peripheral bus function.
SUMMARY OF THE INVENTION
The problems outlined above may at least in part be solved by a computer system including a processor, a memory coupled to the processor, a peripheral bus coupled to the memory and processor as well as a bridge coupled to the peripheral bus. The bridge may comprise a peripheral bus interface coupled to the peripheral bus and a communication controller coupled to the peripheral bus interface. The communication controller may comprise a plurality of buffers each configured to store data, a plurality of bus master engines coupled to the plurality of buffers and a bus interface unit coupled to the plurality of buffers. The plurality of bus master engines may be configured to transfer data between the plurality of buffers and the memory. Furthermore, a plurality of communication medium interfaces may be coupled to the bus interface unit of the communication controller. Each of the plurality of communication medium interfaces may be configured to receive data from a transmission medium and store the data in at least one of the plurality of buffers. Furthermore, each of the plurality of communication medium interfaces may be configured to receive data from at least one of the plurality of buffers and provide the data to the transmission medium.
According to one embodiment of the invention, the bus master engines, buffers and communication medium interfaces are dynamically configurable so that a set or subset of bus master engine(s), buffer(s) and communication medium interface(s) can be used in either a single or multiple peripheral bus function(s). For example, a set of at least one of the plurality of bus master engines and at least one of the plurality of buffers can be used to perform multiple peripheral bus functions that do not operate simultaneously. Furthermore, a set of at least one of the plurality of bus master engines, at least one of the plurality of buffers and at least one of the plurality of communication medium interfaces can be used in multiple peripheral bus functions. Moreover, a plurality of buffers can be used or aggregated together with at least one of the plurality of bus master engines and at least one of the communication medium interfaces to perform a single peripheral bus function. Furthermore, a plurality of bus master engines and/or a plurality of buffers can be used together with at least one of the communication medium interfaces to perform a single peripheral bus function.
REFERENCES:
patent: 6098110 (2000-08-01), Witkowski et al.
patent: 6151644 (2000-11-01), Wu
patent: 6397268 (2002-05-01), Cepulis
Advanced Micro Devices , Inc.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Ray Gopal C.
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