Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2003-04-17
2008-12-30
Patel, Niketa I (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S007000, C710S009000, C710S025000, C710S038000, C710S062000
Reexamination Certificate
active
07472205
ABSTRACT:
A communication controller of the present invention includes a descriptor cache mechanism which makes a virtual descriptor gather list from the descriptor indicted from a host, and which allows a processor to refer to a portion of the virtual descriptor gather list in a descriptor cache window. Another communication controller of the present invention includes a second processor which allocates any communication process related with a first communication unit of the communication processes to the first one of a first processors and any communication process related with a second communication unit of the communication processes to the second one of the first processors. Another communication controller includes a first memory which stores control information. The first memory includes a first area accessed by the associated one of processors to refer to the control information and a second area which stores the control information during the access.
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Dews Brooke J
Foley & Lardner LLP
NEC Corporation
Patel Niketa I
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