Communication clocking conversion techniques

Details Communication clocking conversion techniques Communication clocking conversion techniques

2006-11-07

2006-11-07

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S500000, C326S093000

Reexamination Certificate

active

07134038

ABSTRACT:
A plurality of groups of first flip-flops (group40of flip-flops A1–An−1 for each of channels CIA–CIC) store input data clocked in response to first clock signals (A–C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group60of flip-flops B1–Bn for each of channels CIA–CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group80for each of channels CIA–CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

REFERENCES:
patent: 3631426 (1971-12-01), Appelt et al.
patent: 4607345 (1986-08-01), Mehta
patent: 5425062 (1995-06-01), Boop
patent: 5706438 (1998-01-01), Choi et al.
patent: 6018305 (2000-01-01), Kikuchi et al.
patent: 6480512 (2002-11-01), Ahn

Affiliated with

Also associated with

Rating

Communication clocking conversion techniques does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Communication clocking conversion techniques, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Communication clocking conversion techniques will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3628277