Communication clocking conversion techniques

Details Communication clocking conversion techniques Communication clocking conversion techniques

2005-08-09

2005-08-09

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000, C710S071000, C326S093000, C327S176000

Reexamination Certificate

active

06928573

ABSTRACT:
A plurality of groups of first flip-flops (group40of flip-flops A1-An−1 for each of channels CIA-CIC) store input data clocked in response to first clock signals (A-C). First enable signals (Stack_en) are generated for each group of first flip-flops. A plurality of groups of second flip-flops (group60of flip-flops B1-Bn for each of channels CIA-CIC) store the input data from the first flip-flops in response to the first enable signals and first clock signals. A second enable signal (Slide_en) is generated in response to a second clock signal (D) and the first enable signal. A plurality of groups of third flip-flops (group80for each of channels CIA-CIC) store the data in response to the second enable signal and second clock signal. The data is transmitted in serial form at the rate of the second clock signal.

REFERENCES:
patent: 4607345 (1986-08-01), Mehta
patent: 5425062 (1995-06-01), Boop
patent: 5706438 (1998-01-01), Choi et al.
patent: 6480512 (2002-11-01), Ahn

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