Multiplex communications – Channel assignment techniques – Arbitration for access to a channel
Patent
1995-04-17
1997-02-11
Olms, Douglas W.
Multiplex communications
Channel assignment techniques
Arbitration for access to a channel
370471, H04J 302
Patent
active
056028490
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND TO THE INVENTION
The invention relates to a multistation single-channel communication bus system accommodating master stations and slave stations, any master station comprising arbitration means, arbitration outcome detection means, and formatting means for upon winning said arbitration formatting a frame comprising slave address and slave control signalizations and accommodating a plurality of data byte periods for data transmission from a transmitter station to a receiver station up to a first maximum, and each period accommodating an acknowledge bit from said receiver station, said transmitter station being arranged for upon absence of such acknowledge bit for a particular data byte repeating that data byte. Generally, such comunication systems impose a maximum value on the allowable length of a frame, so that a particular master station cannot keep the whole system engaged for more than a reasonable interval of time. The consequence of this is that if a master station wants to send a long message to a particular slave station, or receive such message from a slave transmitter station, this is done in a sequence of frames that collectively constitute the message. In such case, the master station in question is often enabled to keep an addressed slave station free from accessing by other master stations between successive frames of the message. For this object, the locking mechanism has been proposed, such as described, for example, in U.S. Pat. No. 5,128,936 (PHN 12484) assigned to the assignee of the present application for patent and herein incorporated by reference. In the reference, the transfer reliability is enhanced, in that the receiver station directly after successful reception of a particular data byte responds with an acknowledge bit. If the acknowledge bit does not appear, the transmitter will repeat the data byte in question. The acknowledge bit may be absent for a variety of reasons, such as receive buffer full, parity wrong, or electrical interference. The policy viz a viz slave address and slave control acknowledge is different, but this is ignored here.
Now, the locking and unlocking signalizations are in the head of the frame. This has led to the procedure of transmitting the ultimate data byte of a message, together with the unlocking signalization, in a separate frame. The additional frame causes extra bus load, especially in such cases where the probability that the frame length would actually be exceeded is only small, so that the necessity for the lock is scant. In consequence, for relatively short messages, the locking may be foregone. This however, leads to a new problem, in that the data receiver can only process the message when it has been received completely. However, this completing can be thwarted in various ways, such as by a higher priority master that accesses the same slave, and continually wins the arbitrage. The latter access could effectively be refused by the slave in question, because it is busy. Alternatively, to allow the slave station to converse with two masters in alternation poses a severe bookkeeping requirement to the software. All these problems of course multiply with the number of master stations.
SUMMARY OF THE INVENTION
Therefore, amongst other things, it is an object of the present invention to allow transfer of relatively short messages in a system of the kind considered, wherein the locking mechanism is not necessary, while still maintaining coherence of the complete message without necessitating a complex data management in the receiver. Now, according to one of its aspects, the invention is characterized in that said system is arranged for with respect to intended transfer of a message whose data byte length would exceed said first maximum dividing said message into partial messages each of an associated frame data byte count below said first maximum, and assigning each partial message to a respective bus frame, said system having counting means for counting in a particular frame data byte periods and received acknowledge bits, sai
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patent: 5448593 (1995-09-01), Hill
patent: 5469435 (1995-11-01), Krein et al.
patent: 5473606 (1995-12-01), Hoekstra
D2B Systems Company Limited
Hom Shick
Olms Douglas W.
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