Communication bus for a multi-processor system

Details Communication bus for a multi-processor system Communication bus for a multi-processor system

2000-01-03

2004-05-04

Myers, Paul R. (Department: 2112)

Electrical computers and digital data processing systems: input/

Access arbitrating

Centralized arbitrating

C710S113000

Reexamination Certificate

active

06732210

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to a multiple processing unit system in which the processing units can communicate directly with each other, and more particularly to a novel communication bus and bus protocol which facilitates communication between processing units.
Multi-processor or multi-processing unit systems are well known in the art. To fully utilize the benefits of having multiple processing units working in parallel, the processing units should communicate with one another. However, most bus structures connecting multiple processing units are designed to allow the processing units to share memory, not communicate directly. That is, the busses are memory busses, not communication busses. Memory busses are configured to handle bursts of data efficiently, such as cache lines or other data blocks. In designs in which the memory bus is used to connect processing units to DRAM memory, it also is important to perform longer bursts of data transfer for efficiency, as DRAM has a set-up overhead when accessing an address which is not adjacent to a previously accessed address. This burst nature gives the bus higher bandwidth at a cost of higher latencies.
In certain situations, it is important to have low latency transfers. For example, in a multi-media system performing a 3D pixel rendering function, one processing unit may be configured to process a list of geometry coordinates, while another processing unit may be configured to render the scene on a video display. With the current systems, the first processing unit writes the geometry coordinates to memory, and then the second processing unit pulls the coordinates out of memory to render the scene. With this configuration, the memory buffer decouples the two processes, creating latencies caused by writing data to and reading data from the memory. These latencies reduce the true parallel processing benefits from the multi-processing unit system, because the second processing unit is delayed in rendering the 3D scene. To more efficiently process the data, it is preferable for the first processing unit to pass the data directly to the second processing unit to avoid the memory latencies. That way, the second processing unit can perform the rendering process as soon as possible.
Thus, what is needed is a communication bus and associated protocol that facilitates low latency transfers between multiple processing units.
SUMMARY OF THE INVENTION
In accordance with the invention, a multi-processing unit system including a plurality of processing units in direct communication via a communication bus is presented. The system includes a communication bus arbiter having a communication packet multiplexer. Each of the processing units includes a communication bus interface comprising a transmitter interface and a receiver interface. Each of the transmitter interfaces is connected to the communication packet multiplexer of the communication bus arbiter via separate 32-bit interfaces. Each of the receiver interfaces is connected to the communication packet multiplexer of the communication bus arbiter via a single 32-bit bus.
The system may further comprise a first control signal connection means for communicating control signals between the transmitter interface and the communication bus arbiter and a second control signal connection means for communicating control signal between the receiver interface and the communication bus arbiter. In accordance with one embodiment of the present invention, the first control signal connection means comprises two 1-bit communication connections, one for communicating bus request signals from the transmitter interface to the communication bus arbiter, and the other for communicating bus request acknowledgment signals from the communication bus arbiter to the transmitter interface. Similarly, the second control signal connection means preferably comprises two 1-bit communication connections, one form communicating receiver buffer full signals from the receiver interface to the communication bus arbiter, and the other for communicating receive packet enable signals from the communication bus arbiter to the receiver interface.
In accordance with one embodiment of the present invention, the processing units preferably communicate with one another using communication packets comprising a 32-bit header and a 128-bit data packet. The 128-bit data packet preferably is presented as 4 32-bit data packets.
The present invention further comprises a novel communication protocol for communicating data packets between the processing units over the communication bus. In accordance with one embodiment of the protocol or the present invention, a first processing unit sends a bus request to a bus arbiter. If the communication bus is open for communication, the bus arbiter grants the first processing unit access to the bus. The first processing unit then sends a header packet to the bus arbiter, which includes a target ID. The bus arbiter takes the target ID and determines if a second processing unit associated with the target ID is able to receive data from the first processing unit. If the second processing unit is able to receive data, the first processing unit sends a 128-bit data packet to the bus arbiter, which in turn, sends the data packet to the second processing unit. In accordance with one embodiment of the present invention, the 128-bit data packet is sent in 4 separate 32-bit packets. It typically takes 5 clock cycles to send the 128 bits of data to the second processing unit.


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