Communication between two embedded processors

Details Communication between two embedded processors Communication between two embedded processors

2005-08-02

2005-08-02

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S022000, C710S308000, C709S200000, C714S006130, C714S011000, C714S012000, C714S043000

Reexamination Certificate

active

06925512

ABSTRACT:
A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

REFERENCES:
patent: 4217486 (1980-08-01), Tawfik et al.
patent: 4428044 (1984-01-01), Liron
patent: 4502114 (1985-02-01), Krikor et al.
patent: 5185877 (1993-02-01), Bissett et al.
patent: 5317726 (1994-05-01), Horst
patent: 5446841 (1995-08-01), Kitano et al.
patent: 5590308 (1996-12-01), Shih
patent: 5636361 (1997-06-01), Ingerman
patent: 5923339 (1999-07-01), Date et al.
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6092136 (2000-07-01), Luedtke
patent: 6094710 (2000-07-01), Arimilli et al.
patent: 6101589 (2000-08-01), Fuhrmann et al.
patent: 6119176 (2000-09-01), Maruyama
patent: 6351744 (2002-02-01), Landresse
patent: 6415361 (2002-07-01), Moh et al.
patent: 6526462 (2003-02-01), Elabd
patent: 6647453 (2003-11-01), Duncan et al.
patent: 6651139 (2003-11-01), Ozeki et al.
patent: 6701411 (2004-03-01), Matsunami et al.
patent: 6813652 (2004-11-01), Stadler et al.
patent: 2002/0082716 (2002-06-01), Hashimoto et al.
patent: 2002/0129208 (2002-09-01), Barroso et al.
patent: 2002/0161452 (2002-10-01), Peltier
patent: 2002/0161453 (2002-10-01), Peltier
patent: 2002/0184445 (2002-12-01), Cherabuddi
patent: 2003/0009629 (2003-01-01), Gruner et al.
patent: 2003/0120896 (2003-06-01), Gosior et al.
patent: 2004/0022107 (2004-02-01), Zaidi et al.
patent: 2004/0054855 (2004-03-01), Yasuda et al.
patent: 2004/0172490 (2004-09-01), Stadler et al.
Bisiani, Roberto, et al., “PLUS: A Distributed Shared-Memory System,” May 28-31, 1990, IEEE 17th Annual International Symposium on Computer Architecture, Proceedings, p. 115-124.
Bodnar, B.L., et al., “Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors,” Mar. 1989, IEEE Transactions on Computers, vol. 38, p. 464-470.

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