Communicating between a native fully buffered dual in-line...

Details Communicating between a native fully buffered dual in-line... Communicating between a native fully buffered dual in-line...

2007-04-30

2010-06-15

Phan, Raymond N (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S308000, C710S306000

Reexamination Certificate

active

07739441

ABSTRACT:
A translator of an apparatus in an example communicatively interconnects a serial protocol bus that follows a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol) and three or more parallel protocol memory module channels that comprise a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs).

REFERENCES:
patent: 6215727 (2001-04-01), Parson et al.
patent: 6347367 (2002-02-01), Dell et al.
patent: 6392946 (2002-05-01), Wu et al.
patent: 6467048 (2002-10-01), Olarig et al.
patent: 6507888 (2003-01-01), Wu et al.
patent: 6779075 (2004-08-01), Wu et al.
patent: 6826113 (2004-11-01), Ellis et al.
patent: 7143298 (2006-11-01), Wells et al.
patent: 7379316 (2008-05-01), Rajan
patent: 7475316 (2009-01-01), Cowell et al.
patent: 7532537 (2009-05-01), Solomon et al.
patent: 7539810 (2009-05-01), Gower et al.
patent: 7577039 (2009-08-01), Yang et al.
patent: 2006/0047899 (2006-03-01), Ilda et al.
patent: 2006/0146629 (2006-07-01), Lee
patent: 2006/0155517 (2006-07-01), Dobbs et al.
patent: 2007/0192563 (2007-08-01), Rajan et al.
patent: 2008/0077731 (2008-03-01), Forrest et al.
patent: 2008/0091888 (2008-04-01), Sandy
patent: 2008/0126690 (2008-05-01), Rajan et al.
patent: 2008/0181021 (2008-07-01), Thayer
patent: 2008/0250292 (2008-10-01), Djordjevic
patent: 2008/0256281 (2008-10-01), Fahr et al.
patent: 2009/0101711 (2009-04-01), Grayson
JEDEC Standatd, FBDIMM: Architecture and Protocol, JESD206.PDF© JEDEC Solid State Technology Association 2007, Arlington, Virginia http://www.jedec.org/download/search/JESD206.pdf Section 2.1.3 (AMB addressing) table 2-4 showing the DS [3:0] usage.
Same Document Section 2.1.3 paragraph 3 shows that for DRAM addressing one can only use DS [2:0].
Same Document Section 4.2.3 find the FBD command encoding protocol. This is the same protocol that would be used by disclosure 63, this table also shows the RS (rank selection bit).
Same Document Section 4.2.4 find information on DRAM commands and a DRAM comman mapping example—this section (paragraph 3) explains the use of the RS bit according to the FBD spec.
Same Document Section 4.4.2 gives a write timing example and describes the use of write FIFOs by the AMB.
Same Document Section 4.4.2.1 describes the use of the WS bits according to the FBD protocol.

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