Common wordline flash array architecture

Details Common wordline flash array architecture Common wordline flash array architecture

2006-08-22

2006-08-22

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

Reexamination Certificate

active

07095653

ABSTRACT:
The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder. During erase operations, the p-well of unselected memory array blocks is pulled negative to substantially the same potential as the wordline to avoid erase disturbances. During programming operations, the unselected p-wells are pulled high to avoid gate disturbances.

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