Common source line control circuit for preventing snap back brea

Details Common source line control circuit for preventing snap back brea Common source line control circuit for preventing snap back brea

1996-06-28

1998-05-05

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518525, 36518529, 365218, G11C 1134, G11C 700

Patent

active

057485313

ABSTRACT:
A common source line control circuit for a semiconductor memory device includes a resistor connected in series with a transistor to reduce the voltage across the transistor, thereby preventing snap back breakdown. The resistor and transistor are connected in series with a second transistor which together form a current path between the bulk region of a memory cell array and a ground node for discharging the bulk region during an erase voltage recovery period. The resistor can be connected between the transistors or between one transistor and the bulk region. A second resistor can be connected in series with the other resistor and the two transistors. The resistance values of the resistors are larger than the channel resistances of the transistors.

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