Common modules for DDRII SDRAM and DDRIII SDRAM

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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C326S032000, C326S033000

Reexamination Certificate

active

07825681

ABSTRACT:
A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.

REFERENCES:
patent: 5706447 (1998-01-01), Vivio
patent: 6466472 (2002-10-01), Lin
patent: 6665736 (2003-12-01), Fan
patent: 2002/0144166 (2002-10-01), Chang et al.
patent: 2006/0077731 (2006-04-01), Ware et al.
patent: 2006/0262587 (2006-11-01), Matsui et al.
patent: 2007/0126466 (2007-06-01), Kim

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