Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-06-25
2010-11-02
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S032000, C326S033000
Reexamination Certificate
active
07825681
ABSTRACT:
A common module for a double data rate-synchronous II synchronous dynamic random access memory (DDRII SDRAM) and a DDRIII SDRAM applied in a computer is provided. The common module includes a first bus, a termination circuit card, a first slot, and a second slot. The first bus transmits a plurality of signals. The termination circuit card comprises a plurality of termination resistors. The first slot is disposed on the common module and coupled to the first bus. The DDRII SDRAM is installed in the first slot. The second slot is disposed on the common module and coupled to the first bus. The DDRIII SDRAM or the termination circuit card is installed in the second slot. When the DDRII SDRAM is installed in the first slot, the termination circuit card is installed in the second slot.
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Chen Chin-Hui
Lin Hou-Yuan
Birch & Stewart Kolasch & Birch, LLP
Giga-Byte Technology Co.
Le Don P
Tran Anh Q.
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