Common geometry high voltage tolerant long channel and high spee

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257327, 257368, 257408, 257344, 257346, H01L 2910, H01L 2978, H01L 2968

Patent

active

052570959

ABSTRACT:
A field effect device transistor geometry and method of fabrication are described. The FET may be operated from a bias potential that forms an electrical field within the device exceeding a predetermined field strength. The device comprises a semiconductor substrate portion of a first conductivity type, said substrate portion having a major surface, and a region of a second conductivity type adjacent the major surface and adapted to receive the predetermined bias potential, the region including a subregion of like conductivity type and lesser conductivity, the subregion being positioned within the region such that the subregion receives at least that portion of the dipole electrical field including and exceeding the predetermined value.

REFERENCES:
patent: 3821781 (1974-01-01), Chang et al.
patent: 4072545 (1978-02-01), De La Moneda
patent: 4119995 (1978-10-01), Simko
patent: 4142197 (1979-02-01), Dingwall
patent: 4282648 (1981-09-01), Yu et al.
patent: 4423433 (1983-12-01), Sasahi et al.
patent: 4445267 (1984-08-01), De La Moneda et al.
patent: 4471373 (1984-09-01), Shimizu et al.
patent: 4509067 (1985-07-01), Minami et al.
patent: 4514747 (1985-07-01), Niyata et al.
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4590663 (1986-05-01), Haken
patent: 4590665 (1986-05-01), Owens et al.
patent: 4656492 (1987-07-01), Sunami et al.
patent: 4663645 (1987-05-01), Komori et al.
S. Ogura et al "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE Journal of Solid-State Circuits, vol. SC-15 (1980) pp. 424-432.
A. G. Fortino et al, "Method of Making a Submicron Field-Effect Transistor", IBM Technical Disclosure Bulletin, vol. 23 (1980) pp. 534-536.
S. M. Sze, Semiconductor Devices, Physics and Technology, John Wiley & Sons, New York (1985) pp. 392-395.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Common geometry high voltage tolerant long channel and high spee does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Common geometry high voltage tolerant long channel and high spee, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Common geometry high voltage tolerant long channel and high spee will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-962954

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.