Common domino circuit evaluation device

Details Common domino circuit evaluation device Common domino circuit evaluation device

1998-02-11

2000-08-15

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 83, 326112, H03K 19096, H03K 19094

Patent

active

061042129

ABSTRACT:
A domino CMOS circuit has a number of domino gates, a common virtual ground node and a common evaluation NFET device. Each domino gate provides a PFET precharge device, an NFET device tree, an output inverter stage, a dynamic node, a plurality of input nodes, a clock input node and an output node. The PFET precharge device is coupled to a high voltage supply rail, the clock input node and the dynamic node and an NFET device tree is coupled to the common virtual ground node, to the plurality of inputs and to the dynamic node. An output inverter stage is coupled to the high voltage supply rail, to said dynamic node, to a low voltage supply rail and to said output node. And for improving performance, a common evaluation NFET device is coupled to said clock inputnode, to the to said low voltage supply rail and to the common virtual ground node. The virtual ground node is coupled to the low voltage supply rail when a high voltage is applied to clock input node.

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