Common clock path pessimism analysis for circuit designs...

Details Common clock path pessimism analysis for circuit designs... Common clock path pessimism analysis for circuit designs...

2011-04-12

2011-04-12

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S108000

Reexamination Certificate

active

07926019

ABSTRACT:
Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism. The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.

REFERENCES:
patent: 5636372 (1997-06-01), Hathaway et al.
patent: 7406669 (2008-07-01), Lindberg
patent: 7694254 (2010-04-01), Gregerson et al.
patent: 2005/0066297 (2005-03-01), Kalafala et al.
patent: 2005/0183051 (2005-08-01), Darsow et al.
patent: 2005/0278672 (2005-12-01), Hosono et al.
patent: 2006/0248485 (2006-11-01), Foreman et al.
patent: 2007/0022397 (2007-01-01), Darsow et al.
patent: 2008/0163147 (2008-07-01), Gregerson et al.
patent: 2008/0168412 (2008-07-01), Cheon et al.

Affiliated with

Also associated with

Rating

Common clock path pessimism analysis for circuit designs... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Common clock path pessimism analysis for circuit designs..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Common clock path pessimism analysis for circuit designs... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2662528