Common circuit for dynamic memory refresh and system clock funct

Details Common circuit for dynamic memory refresh and system clock funct Common circuit for dynamic memory refresh and system clock funct

1982-04-07

1985-03-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 700

Patent

active

045035253

ABSTRACT:
A time-of-day counter having a plurality of register stages for counting system clock pulses and for providing signals indicative of the status of each of the register stages is coupled by a bus to a dynamic memory of the type requiring a refresh cycle. Logic means operatively coupled to the time-of-day counter operate to pass the signals present at the output of the time-of-day registers onto the bus as memory address signals so as to effectively utilize the output signals of the time-of-day counter to periodically address all portions of the memory and to provide a refresh signal as each portion of the memory is addressed.

REFERENCES:
patent: 4084154 (1978-04-01), Panigrahi
patent: 4207618 (1980-06-01), White, Jr. et al.
patent: 4249247 (1981-02-01), Patel

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