Common case optimized circuit structure for high-performance...

Details Common case optimized circuit structure for high-performance... Common case optimized circuit structure for high-performance...

1999-06-09

2001-08-14

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06275969

ABSTRACT:

I. DESCRIPTION OF THE INVENTION
IA. Field of the Invention
This invention is related to high-performance low-power VLSI designs. Specifically, the present invention is related to a common case computation (CCC) optimized circuit structure. The present invention is embodied in a computation circuit with reduced power consumption. This Application is related to the concurrently filed U.S. application Ser. No. 09/328,897, by Lakshminarayana et, al.
IB. Background of the Invention
It is a well-known fact that in behavioral descriptions of hardware circuits, a small set of computations, the common case computations (CCCs) often account for most of the computational complexity. This is also true for software programs. However, in the hardware implementations (structural level, RTL level or lower level), the common case computations and the remaining computations are typically treated alike.
Various conventional low-power and high-performance circuit architectures have been proposed at various levels of design abstraction. These include:
Parallel and pipelined circuit architectures for high-performance circuits and low-power circuits. See D. A. Patterson and J. L. Hennessy,
Computer Architecture: A Quantitative Approach
. Morgan Kaufman Publishers. San Mateo, Calif., 1989; See A. R. Chandrakasan and R. W. Brodersen,
Low Power Digital CMOS Design. Kluwer Academic Publishers, Norwell, Mass.
1995.
Gated clock architectures that have reduced power consumption by eliminating unnecessary signal transitions in the clock network and registers. See L. Benini, P. Siegel, and G. DeMicheli, “Saving power by synthesizing gated clocks for sequential circuits,”
IEEE Design
&
Test of Computers
, pp. 32-41, Winter 1994; and L. Benini and G. DeMicheli, “Automatic synthesis of gated-clock sequential circuits,”
IEEE Trans. Computer
-
Aided Design
. vol. 15, pp. 630-643, June 1996.
Pre-computation architectures that compose a circuit block with predictor circuits that are then used to disable the original circuit and reduce power consumption. See M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, “Precomputation-based sequential logic optimization for low power,”
IEEE Trans. VLSI Systems
, vol. 2. pp. 426-436. December 1994.
Telescopic unit architectures for variable latency pipeline stages. See L. Benini. F. Macu, M. Poncino, and G. De Micheli. “Telescopic units: A new paradigm for performance optimization of VLSI designs,”
IEEE Trans. Computer
-
Aided Design
, vol. 17, pp. 220-232, March 1998.
Operand isolation architectures that include transparent latches at the inputs of selected embedded logic blocks, and additional control circuitry to detect idle conditions for the logic block. See A. Correale Jr. Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded processors,” in
Proc. mt. Symp. Low Power Design, pp.
75-80, April 1995; V. Tiwari, S. Malik, and P. Ashar, “Guarded evaluation: Pushing power management to logic synthesis/design,” in
Proc. Int. Syrnp. Low Power Design
. pp. 221-226, April 1995; and J. Mouteiro, J. Rinderknecht, S. Devadas, and A.
Ghosh, Optimization of combinational and sequential logic circuits for low power using precomputation.” in
Proc. Chapel Hill Conf. Advanced Research VLSI
, pp. 430-444. March 1995. The additional control circuitry disables the transparent latches at a logic block's inputs from unnecessarily changing values when the logic block is idle.
It is well known that providing the flexibility of affecting or performing design decisions at the higher levels of design hierarchy, to a designer or a CAD tool, can lead to realizing larger savings in power consumption. See A. R. Chandrakasan and R. W. Brodersen,
Low Power Digital CMOS Design
. Kluwer Academic Publishers, Norwell, Mass., 1995; Rabaey and M. Pedram (Editors),
Low Power Design Methodologies
. Kluwer Academic Publishers, Norwell, Mass., 1996; L. Benini and G. De Micheli,
Dynamic Power Management: Design Techniques and CAD Tools
. Kluwer Academic Publishers, Norwell, Mass., 1997; and A. Raghunathan, N. K. Jha, and S. Dey,
High
-
level Power Analysis and Optimization
. Kluwer Academic Publishers, Norwell, Mass., 1998. Recognizing this fact, various low-power design and CAD techniques have been proposed at the register-transfer, behavior, and system levels. These techniques include:
logic synthesis for low power techniques See J. Rabaey and M. Pedram (Editors), Low Power Design Methodologies. Kluwer Academic Publishers, Norwell, Mass., 1996; S. Devadas and S. Malik, “A survey of optimization techniques targeting low power VLSI circuits,” in Proc. Design Automation Conf., pp. 242-247, June 1995 and J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits, Kluwer Academic Publishers, Norwell, Mass., 1996.
RTL transformations to optimize power. See A. Raghunathan, S. Dey, and N. K. Jha, “Glitch analysis and reduction in register-transfer-level power optimization,” in
Proc. Design Automation Con
!., pp. 331-336, June 1996; and M. Ohnishi, A. Yamada, H. Nods, and T. Kambe, “A method of redundant clocking detection and power reduction at RT level design,” in
Proc. int. Symp. Low Power Electronics
&
Design, pp.
131-136, August 1997;
techniques to perform the conventional high-level synthesis tasks targeting low power dissipation. See A. R. Chandrakasan and R. W. Brodersen,
Low Power Digital CMOS Design
. Kluwer Academic Publishers, Norwell, Mass., 1995; and Rabaey and M. Pedram (Editors),
Low Power Design Methodologies
. Kluwer Academic Publishers, Norwell, Mass., 1996; and A. Raghunathan, N. K. Jha, and S. Dey,
High
-
level Power Analysis and Optimization
. Kluwer Academic Publishers, Norwell, Mass., 1998; and
techniques to apply power management (elimination of idle circuit activity) at the RTL and during high-level synthesis. See L. Benini and G. De Micheli,
Dynamic Power Management: Design Techniques and CAD Tools
. Kluwer Academic Publishers, Norwell, Mass., 1997; and A. Raghunathan, N. K. Jha, and S. Dey,
High
-
level Power Analysis and Optimization
. Kluwer Academic Publishers, Norwell, Mass., 1998.
In an implementation derived without particular attention to the common case, the delay and power expended in executing the CCCs may be significantly higher than necessary due to one or more of the following factors:
Various synthesis optimizations, which may not be applicable in the context of the complete design, are applicable when only the CCCs are considered. For example, a CCC typically consists of only one or a few (conditional) threads of execution from the original behavior. Thus, a substantial quantity of control-flow constructs, which are known to be bottlenecks for various high-level optimizations are eliminated by considering the CCC alone. See D. D Gajski, N. D. Dutt, A. C. -H. Wu, and S. Y. -L. Lin,
High
-
level Synthesis: Introduction to Chip and System Design
. Kluwer Academic Publishers, Norwell, Mass., 1992; and G. De Micheli,
Synthesis and Optimization of Digital Circuits
. McGraw-Hill, New York, N.Y., 1994.
In conventional implementations, sharing of CCC operations with non-CCC operations may result in a significant amount of additional circuitry and parasitics being associated with the execution of CCCs (e.g., additional multiplexers and control circuitry, and larger clock networks and global buses). A separate implementation of the CCC alone would avoid these above problems.
It is well known that a significant fraction of (dynamic) power consumed in typical circuits is due to switching activity in unused circuitry. Although various power management techniques have been proposed to reduce such unnecessary power, they do not guarantee its elimination, and themselves incur overheads by inserting additional circuitry. See L. Benini and G. De Micheli,
Dynamic Power Management: Design Techniques and CAD Tools
. Kluwer Academic Publishers, Norwell, Mass., 1997; A. Raghunathan, N. K. Jha, and S. Dey,
High
-
level Power Analysis and Optimization
. Kluwer Academic Publis

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