Common-bias and differential structure based DLL

Details Common-bias and differential structure based DLL Common-bias and differential structure based DLL

2000-09-06

2004-12-14

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06831492

ABSTRACT:

BACKGROUND
The present invention relates generally to delay-locked loop (DLL) circuits. More particularly, this invention relates to a DLL circuit which utilizes a single common-bias generator to supply the bias voltages and current for a plurality of delay cells.
Delay-locked loops are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. The maintenance of the timing throughout a circuit is important. Timing becomes even more critical in applications requiring high-speed processing of information, such as with video processors. An example of its importance is recognized in a memory read/write circuit. The synchronization of the signal which opens the memory cell with the signal carrying the information to be read from memory or written to memory must be achieved with a certain tolerance. If these two signals are not in sync, the information to be read or written may be lost or corrupted.
The timing throughout a circuit deviates from the system clock when noise is introduced by various system components and capacitive effects due to system interconnections. In recent years, the demand has risen for devices requiring high-speed processing. As a result, the demand for DLL circuits that quickly compensate for electronic noise and capacitive delays has also risen. The problem is that the amount of phase shift produced as a result of the supply, substrate noise and capacitor load is directly related to how quickly the DLL can correct the output frequency.
A design used by those skilled in the art to eliminate the noise present in the circuit at the required speed utilizes a self-bias signal technique. Referring to
FIG. 1A
, this prior art DLL circuit is a self-biasing configuration which uses a differential buffer delay cell, containing a source coupled pair with resistive loads elements called symmetric loads which causes a nonlinear delay with respect to a low pass output voltage shown in FIG.
1
B. The resistance of these symmetric loads is adjusted by the bias circuit to obtain a certain voltage level across them. Therefore, this configuration requires that a symmetric load be used for each separate delay cell present in the DLL circuit.
The problem with this is that it requires the control of a plurality of symmetric loads, which makes the circuit more complicated and more difficult to control. Another problem with the use of a plurality of symmetric loads is that they require the use of more space. Since the cost of a silicon chip is largely dependent upon the number of components on a chip which affects the size of the chip, a larger chip leads to higher costs for the chip.
Accordingly, there exists a need for a DLL circuit which is easier to control, requires less space and produces less electronic noise.
SUMMARY
The present invention comprises a DLL having a plurality of delay elements and a common bias generator. The DLL includes a phase detector for detecting a phase shift between a reference frequency and an output frequency and produces an error signal. A low pass filter filters the error signal, which is input to the common-bias generator. The bias generator generates a common bias voltage pair to selectively control the plurality of delay elements.


REFERENCES:
patent: 5600284 (1997-02-01), Nguyen et al.
patent: 5727037 (1998-03-01), Maneatis
patent: 6094103 (2000-07-01), Jeong et al.
Johns et al., “Analog Integrated Circuit Design”, 1997, Canada, Chapter 16, pp. 675-679.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid State Circuits, vol. 31, No. 11, pp. 1723-1732, Nov. 1996.
Baker et al., “CMOS Circuit Design, Layout, and Simulation”, 1998, Chapter 19, pp. 417-423.

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