Testing circuit and method for phase-locked loop

Details Testing circuit and method for phase-locked loop Testing circuit and method for phase-locked loop

2002-07-30

2004-12-14

Nghiem, Michael (Department: 2863)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Signal frequency or phase correction

C327S157000, C331S016000, C375S130000, C375S376000

Reexamination Certificate

active

06832173

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to phase-locked loops. More particularly, this invention relates to a method and apparatus for testing a phase-locked loop, and to circuitry for facilitating such testing.
The use of phase-locked loops for generating clock and frequency standards is well known. At its most basic, a phase-locked loop (“PLL”) includes, in series, a phase-frequency detector having a first input to which a reference frequency is applied, a charge pump, a loop filter and a voltage-controlled oscillator (“VCO”). The output of the VCO, which is the output of the PLL, is fed back to a second input of the phase-frequency detector. Any phase variance between the reference signal and the feedback signal causes the phase-frequency detector to generate a voltage which is input to the charge pump and loop filter, which output a control voltage to the voltage-controlled oscillator. The PLL output signal keeps changing as the control voltage changes until there is a match between the frequencies of the output and the reference signal, which is detected by the phase-frequency detector. At that point, the PLL is considered to be locked.
Known methods for testing a PLL test whether or not the PLL is capable of locking on a reference signal. However, even if the PLL locks, it may nevertheless be subject to drift if there is excessive leakage current in, e.g., the charge pump or the loop filter, resulting in a phase variance between the input signal and the output signal. It would be desirable to be able to provide a method for testing a PLL that would be capable of detecting such leakage currents or their effects, apparatus for performing such a test and a PLL adapted for such a test.
SUMMARY OF THE INVENTION
It is an advantage of the present invention that it provides a method for testing a PLL that would be capable of detecting such leakage currents or their effects, apparatus for performing such a test and a PLL adapted for such a test.
In accordance with the present invention, there is provided a method of testing a phase-locked loop. The method includes inputting a reference signal to the phase-locked loop, allowing the phase-locked loop to lock onto the reference signal, discontinuing feeding back of the loop output, and monitoring the loop output, after the discontinuing, for a change in the output frequency. Apparatus for performing such a test, and a phase-locked loop adapted to be so tested, are also provided.


REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 4633488 (1986-12-01), Shaw
patent: 4719593 (1988-01-01), Threewitt et al.
patent: 4868522 (1989-09-01), Popat et al.
patent: 4959646 (1990-09-01), Podkowa et al.
patent: 5072195 (1991-12-01), Graham et al.
patent: 5075575 (1991-12-01), Shizukuishi et al.
patent: 5079519 (1992-01-01), Ashby et al.
patent: 5133064 (1992-07-01), Hotta et al.
patent: 5204555 (1993-04-01), Graham et al.
patent: 5349544 (1994-09-01), Wright et al.
patent: 5397943 (1995-03-01), West et al.
patent: 5418499 (1995-05-01), Nakao
patent: 5420544 (1995-05-01), Ishibashi
patent: 5506878 (1996-04-01), Chiang
patent: 5542083 (1996-07-01), Hotta et al.
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5656959 (1997-08-01), Chang et al.
patent: 5699020 (1997-12-01), Jefferson
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5744991 (1998-04-01), Jefferson et al.
patent: RE35797 (1998-05-01), Graham et al.
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5815016 (1998-09-01), Erickson
patent: 5847617 (1998-12-01), Reddy et al.
patent: 5900757 (1999-05-01), Aggarwal et al.
patent: 5987543 (1999-11-01), Smith
patent: 6014048 (2000-01-01), Talaga, Jr. et al.
patent: 6069506 (2000-05-01), Miller, Jr. et al.
patent: 6069507 (2000-05-01), Shen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6292507 (2001-09-01), Hardin et al.
patent: 6373278 (2002-04-01), Sung et al.
patent: 6396889 (2002-05-01), Sunter et al.
patent: 6400129 (2002-06-01), Yamaguchi et al.
patent: 6624705 (2003-09-01), Huard et al.
patent: 6628739 (2003-09-01), Hayashi
patent: 6633185 (2003-10-01), Starr
patent: 2003/0119466 (2003-06-01), Goldman
patent: 0 266 065 (1988-05-01), None
patent: 0 416 930 (1991-03-01), None
patent: 0 778 517 (1997-06-01), None
patent: 1-137646 (1989-05-01), None
DynaChip Corp., DY6000 Family Datasheet (Dec. 1998).
Ko, U., et al., “A 30-ps Jitter, 3.6 &mgr;s Locking, 3.3-Volt Digital PLL for CMOS Gate Arrays,”Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, Publication No. 0-7803-0826-3/93, pp. 23.3.1-23.3.4 (May 9-12, 1993).
LSI Logic Corp., 500K Technology Design Manual (Document DB04-000062-00, First Edition), pp. 8-1—8-33 (Dec. 1996).
Advanced Micro Devices, Inc., “Am2971 Programmable Event Generator (PEG),” Publication No. 05280, Rev. C, Amendment /0, pp. 4-286—4-303 (Jul. 1986).
Advanced Micro Devices, Inc., “AmPAL*23S8 20-Pin IMOX PAL-Based Sequencer,” Publication No. 06207, Rev. B, Amendment /0, pp. 4-102—4-121 (Oct. 1986).
DynaChip Corp., “Application Note: Using Phase Locked Loops in DL6035 Devices” (1998).
Lucent Technologies, Inc., Optimized Reconfigurable Cell Array (ORCA™) OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, (Nov. 1997).
Lucent Technologies, Inc., ORCA® Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01 (Aug. 1998).
Monolithic Memories, Inc., “Programmable Array Logic PAL20RA10-20 Advance Information,” pp. 5-95—5-102 (Jan. 1988).
National Semiconductor Corp.,LVDS Owner's Manual & Design Guide(Apr. 25, 1997).
National Semiconductor Corp., “DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHZ,” (Mar. 1998).
Xilinx, Inc., Virtex 2.5V Field Programmable Gate Arrays Advance Product Specification (Version 1.0) (Oct. 20, 1998).
Xilinx, Inc., Application Note: Using the Virtex Delay-Locked Loop (Version 1.31) (Oct. 21, 1998).
Zaks, R., et al.,From Chips to Systems: An Introduction to Microcomputers,pp. 54-61 (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1987).

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