Command scheduling and affiliation management for serial...

Details Command scheduling and affiliation management for serial... Command scheduling and affiliation management for serial...

2005-09-27

2009-11-17

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S005000, C710S006000, C710S008000, C710S011000, C710S062000

Reexamination Certificate

active

07620751

ABSTRACT:
According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

REFERENCES:
patent: 6134617 (2000-10-01), Weber
patent: 6434590 (2002-08-01), Blelloch et al.
patent: 6493782 (2002-12-01), Verdun et al.
patent: 6917992 (2005-07-01), Grimsrud
patent: 2002/0138670 (2002-09-01), Johnson
patent: 2003/0056034 (2003-03-01), Olds et al.
patent: 2005/0166014 (2005-07-01), Kobayashi et al.
Intel Corporation, “Serial ATA II Native Command Queuing Overview”, Apr. 2003, 21 pages.

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